Commit b8925ee2 authored by Will Deacon's avatar Will Deacon Committed by Catalin Marinas
Browse files

arm64: cpu: Move errata and feature enable callbacks closer to callers 



The cpu errata and feature enable callbacks are only called via their
respective arm64_cpu_capabilities structure and therefore shouldn't
exist in the global namespace.

Move the PAN, RAS and cache maintenance emulation enable callbacks into
the same files as their corresponding arm64_cpu_capabilities structures,
making them static in the process.

Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 7c36447a

arch/arm64/include/asm/processor.h

+0 −4
Original line number Diff line number Diff line
@@ -251,10 +251,6 @@ static inline void spin_lock_prefetch(const void *ptr) 


#endif



void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused);

void cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused);

void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused);



extern unsigned long __ro_after_init signal_minsigstksz; /* sigframe size */

extern void __init minsigstksz_setup(void);

arch/arm64/kernel/cpu_errata.c

+6 −0
Original line number Diff line number Diff line
@@ -433,6 +433,12 @@ out_printmsg: 
}

#endif	/* CONFIG_ARM64_SSBD */



static void __maybe_unused

cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused)

{

	sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0);

}



#define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)	\

	.matches = is_affected_midr_range,			\

	.midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max)

arch/arm64/kernel/cpufeature.c

+22 −6
Original line number Diff line number Diff line
@@ -1081,6 +1081,28 @@ static void cpu_enable_ssbs(const struct arm64_cpu_capabilities *__unused) 
}

#endif /* CONFIG_ARM64_SSBD */



#ifdef CONFIG_ARM64_PAN

static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)

{

	/*

	 * We modify PSTATE. This won't work from irq context as the PSTATE

	 * is discarded once we return from the exception.

	 */

	WARN_ON_ONCE(in_interrupt());



	sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);

	asm(SET_PSTATE_PAN(1));

}

#endif /* CONFIG_ARM64_PAN */



#ifdef CONFIG_ARM64_RAS_EXTN

static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)

{

	/* Firmware may have left a deferred SError in this register. */

	write_sysreg_s(0, SYS_DISR_EL1);

}

#endif /* CONFIG_ARM64_RAS_EXTN */



static const struct arm64_cpu_capabilities arm64_features[] = {

	{

		.desc = "GIC system register CPU interface",
@@ -1824,9 +1846,3 @@ static int __init enable_mrs_emulation(void) 
}



core_initcall(enable_mrs_emulation);
 


void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)

{

	/* Firmware may have left a deferred SError in this register. */

	write_sysreg_s(0, SYS_DISR_EL1);

}

arch/arm64/kernel/traps.c

+0 −5
Original line number Diff line number Diff line
@@ -412,11 +412,6 @@ asmlinkage void __exception do_undefinstr(struct pt_regs *regs) 
	BUG_ON(!user_mode(regs));

}



void cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused)

{

	sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0);

}



#define __user_cache_maint(insn, address, res)			\

	if (address >= user_addr_max()) {			\

		res = -EFAULT;					\

arch/arm64/mm/fault.c

+0 −14
Original line number Diff line number Diff line
@@ -864,17 +864,3 @@ asmlinkage int __exception do_debug_exception(unsigned long addr, 
	return rv;

}

NOKPROBE_SYMBOL(do_debug_exception);
 


#ifdef CONFIG_ARM64_PAN

void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)

{

	/*

	 * We modify PSTATE. This won't work from irq context as the PSTATE

	 * is discarded once we return from the exception.

	 */

	WARN_ON_ONCE(in_interrupt());



	sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);

	asm(SET_PSTATE_PAN(1));

}

#endif /* CONFIG_ARM64_PAN */

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