Commit b8889c4f authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'tty-4.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty 

Pull tty driver reverts from Greg KH:
 "Here are some reverts for some tty patches (specifically the pl011
  driver) that ended up breaking a bunch of machines (i.e. almost all
  of the ones with this chip).

  People are working on a fix for this, but in the meantime, it's best
  to just revert all 5 patches to restore people's serial consoles.

  These reverts have been in linux-next for many days now"

* tag 'tty-4.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty:
  Revert "uart: pl011: Rename regs with enumeration"
  Revert "uart: pl011: Introduce register accessor"
  Revert "uart: pl011: Introduce register look up table"
  Revert "uart: pl011: Improve LCRH register access decision"
  Revert "uart: pl011: Add support to ZTE ZX296702 uart"
parents fac33bfd 0de6cfb9

drivers/tty/serial/Kconfig

+2 −2
Original line number Diff line number Diff line
@@ -47,12 +47,12 @@ config SERIAL_AMBA_PL010_CONSOLE 


config SERIAL_AMBA_PL011

	tristate "ARM AMBA PL011 serial port support"

	depends on ARM_AMBA || SOC_ZX296702

	depends on ARM_AMBA

	select SERIAL_CORE

	help

	  This selects the ARM(R) AMBA(R) PrimeCell PL011 UART.  If you have

	  an Integrator/PP2, Integrator/CP or Versatile platform, say Y or M

	  here. Say Y or M if you have SOC_ZX296702.

	  here.



	  If unsure, say N.

drivers/tty/serial/amba-pl011.c

+123 −380

File changed.

Preview size limit exceeded, changes collapsed.

include/linux/amba/serial.h

+0 −14
Original line number Diff line number Diff line
@@ -33,14 +33,12 @@ 
#define UART01x_DR		0x00	/* Data read or written from the interface. */

#define UART01x_RSR		0x04	/* Receive status register (Read). */

#define UART01x_ECR		0x04	/* Error clear register (Write). */

#define ZX_UART01x_DR		0x04	/* Data read or written from the interface. */

#define UART010_LCRH		0x08	/* Line control register, high byte. */

#define ST_UART011_DMAWM	0x08    /* DMA watermark configure register. */

#define UART010_LCRM		0x0C	/* Line control register, middle byte. */

#define ST_UART011_TIMEOUT	0x0C    /* Timeout period register. */

#define UART010_LCRL		0x10	/* Line control register, low byte. */

#define UART010_CR		0x14	/* Control register. */

#define ZX_UART01x_FR		0x14	/* Flag register (Read only). */

#define UART01x_FR		0x18	/* Flag register (Read only). */

#define UART010_IIR		0x1C	/* Interrupt identification register (Read). */

#define UART010_ICR		0x1C	/* Interrupt clear register (Write). */
@@ -51,21 +49,13 @@ 
#define UART011_LCRH		0x2c	/* Line control register. */

#define ST_UART011_LCRH_TX	0x2c    /* Tx Line control register. */

#define UART011_CR		0x30	/* Control register. */

#define ZX_UART011_LCRH_TX	0x30    /* Tx Line control register. */

#define UART011_IFLS		0x34	/* Interrupt fifo level select. */

#define ZX_UART011_CR		0x34	/* Control register. */

#define ZX_UART011_IFLS		0x38	/* Interrupt fifo level select. */

#define UART011_IMSC		0x38	/* Interrupt mask. */

#define UART011_RIS		0x3c	/* Raw interrupt status. */

#define UART011_MIS		0x40	/* Masked interrupt status. */

#define ZX_UART011_IMSC		0x40	/* Interrupt mask. */

#define UART011_ICR		0x44	/* Interrupt clear register. */

#define ZX_UART011_RIS		0x44	/* Raw interrupt status. */

#define UART011_DMACR		0x48	/* DMA control register. */

#define ZX_UART011_MIS		0x48	/* Masked interrupt status. */

#define ZX_UART011_ICR		0x4c	/* Interrupt clear register. */

#define ST_UART011_XFCR		0x50	/* XON/XOFF control register. */

#define ZX_UART011_DMACR	0x50	/* DMA control register. */

#define ST_UART011_XON1		0x54	/* XON1 register. */

#define ST_UART011_XON2		0x58	/* XON2 register. */

#define ST_UART011_XOFF1	0x5C	/* XON1 register. */
@@ -85,19 +75,15 @@ 
#define UART01x_RSR_PE 		0x02

#define UART01x_RSR_FE 		0x01



#define ZX_UART01x_FR_BUSY	0x300

#define UART011_FR_RI		0x100

#define UART011_FR_TXFE		0x080

#define UART011_FR_RXFF		0x040

#define UART01x_FR_TXFF		0x020

#define UART01x_FR_RXFE		0x010

#define UART01x_FR_BUSY		0x008

#define ZX_UART01x_FR_DSR       0x008

#define UART01x_FR_DCD 		0x004

#define UART01x_FR_DSR 		0x002

#define ZX_UART01x_FR_CTS	0x002

#define UART01x_FR_CTS 		0x001

#define ZX_UART011_FR_RI	0x001

#define UART01x_FR_TMSK		(UART01x_FR_TXFF + UART01x_FR_BUSY)



#define UART011_CR_CTSEN	0x8000	/* CTS hardware flow control */

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