dt-bindings: Convert Faraday FTIDE010 to DT schema

* Faraday Technology FTIDE010 PATA controller

This controller is the first Faraday IDE interface block, used in the

StorLink SL2312 and SL3516, later known as the Cortina Systems Gemini

platform. The controller can do PIO modes 0 through 4, Multi-word DMA

(MWDM)modes 0 through 2 and Ultra DMA modes 0 through 6.

On the Gemini platform, this PATA block is accompanied by a PATA to

SATA bridge in order to support SATA. This is why a phandle to that

controller is compulsory on that platform.

The timing properties are unique per-SoC, not per-board.

Required properties:

- compatible: should be one of

  "cortina,gemini-pata", "faraday,ftide010"

  "faraday,ftide010"

- interrupts: interrupt for the block

- reg: registers and size for the block

Optional properties:

- clocks: a SoC clock running the peripheral.

- clock-names: should be set to "PCLK" for the peripheral clock.

Required properties for "cortina,gemini-pata" compatible:

- sata: a phande to the Gemini PATA to SATA bridge, see

  cortina,gemini-sata-bridge.txt for details.

Example:

ata@63000000 {

	compatible = "cortina,gemini-pata", "faraday,ftide010";

	reg = <0x63000000 0x100>;

	interrupts = <4 IRQ_TYPE_EDGE_RISING>;

	clocks = <&gcc GEMINI_CLK_GATE_IDE>;

	clock-names = "PCLK";

	sata = <&sata>;

};

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/ata/faraday,ftide010.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Faraday Technology FTIDE010 PATA controller

maintainers:

  - Linus Walleij <linus.walleij@linaro.org>

description: |

  This controller is the first Faraday IDE interface block, used in the

  StorLink SL3512 and SL3516, later known as the Cortina Systems Gemini

  platform. The controller can do PIO modes 0 through 4, Multi-word DMA

  (MWDM) modes 0 through 2 and Ultra DMA modes 0 through 6.

  On the Gemini platform, this PATA block is accompanied by a PATA to

  SATA bridge in order to support SATA. This is why a phandle to that

  controller is compulsory on that platform.

  The timing properties are unique per-SoC, not per-board.

properties:

  compatible:

    oneOf:

      - const: faraday,ftide010

      - items:

        - const: cortina,gemini-pata

        - const: faraday,ftide010

  reg:

    maxItems: 1

  interrupts:

    maxItems: 1

  clocks:

    minItems: 1

  clock-names:

    const: PCLK

  sata:

    description:

      phandle to the Gemini PATA to SATA bridge, if available

    $ref: /schemas/types.yaml#/definitions/phandle

required:

  - compatible

  - reg

  - interrupts

allOf:

  - $ref: pata-common.yaml#

  - if:

      properties:

        compatible:

          contains:

            const: cortina,gemini-pata

    then:

      required:

        - sata

examples:

  - |

    #include <dt-bindings/interrupt-controller/irq.h>

    #include <dt-bindings/clock/cortina,gemini-clock.h>

    ide@63000000 {

      compatible = "cortina,gemini-pata", "faraday,ftide010";

      reg = <0x63000000 0x100>;

      interrupts = <4 IRQ_TYPE_EDGE_RISING>;

      clocks = <&gcc GEMINI_CLK_GATE_IDE>;

      clock-names = "PCLK";

      sata = <&sata>;

      #address-cells = <1>;

      #size-cells = <0>;

      ide-port@0 {

        reg = <0>;

      };

      ide-port@1 {

        reg = <1>;

      };

    };

...