Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Imagination University Program MIPSfpga

=======================================

Under the Imagination University Program, a microAptiv UP core has been

released for academic usage.

As we are dealing with a MIPS core instantiated on an FPGA, specifications

are fluid and can be varied in RTL.

This binding document is provided as baseline guidance for the example

project provided by IMG.

The example project runs on the Nexys4DDR board by Digilent powered by

the ARTIX-7 FPGA by Xilinx.

Relevant details about the example project and the Nexys4DDR board:

- microAptiv UP core m14Kc

- 50MHz clock speed

- 128Mbyte DDR RAM	at 0x0000_0000

- 8Kbyte RAM		at 0x1000_0000

- axi_intc		at 0x1020_0000

- axi_uart16550		at 0x1040_0000

- axi_gpio		at 0x1060_0000

- axi_i2c		at 0x10A0_0000

- custom_gpio		at 0x10C0_0000

- axi_ethernetlite	at 0x10E0_0000

- 8Kbyte BootRAM	at 0x1FC0_0000

Required properties:

--------------------

 - compatible: Must include "digilent,nexys4ddr","img,xilfpga".

CPU nodes:

----------

A "cpus" node is required.  Required properties:

 - #address-cells: Must be 1.

 - #size-cells: Must be 0.

A CPU sub-node is also required for at least CPU 0. Required properties:

 - device_type: Must be "cpu".

 - compatible: Must be "mips,m14Kc".

 - reg: Must be <0>.

 - clocks: phandle to ext clock for fixed-clock received by MIPS core.

Example:

	compatible = "img,xilfpga","digilent,nexys4ddr";

	cpus {

		#address-cells = <1>;

		#size-cells = <0>;

		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "mips,m14Kc";

			reg = <0>;

			clocks	= <&ext>;

		};

	};

	ext: ext {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <50000000>;

	};

Boot protocol:

--------------

The BootRAM is a writeable "RAM" in FPGA at 0x1FC0_0000.

This is for easy reprogrammibility via JTAG.

The BootRAM initializes the cache and the axi_uart peripheral.

DDR initialization is already handled by a HW IP block.

When the example project bitstream is loaded, the cpu_reset button

needs to be pressed.

The bootram initializes the cache and axi_uart.

Then outputs MIPSFPGA\n\r on the serial port on the Nexys4DDR board.

At this point, the board is ready to load the Linux kernel

vmlinux file via JTAG.

obj-y += kernel/

obj-y += mm/

obj-y += net/

obj-y += vdso/

ifdef CONFIG_KVM

obj-y += kvm/

platforms += sni

platforms += txx9

platforms += vr41xx

platforms += xilfpga

# include the platform specific files

include $(patsubst %, $(srctree)/arch/mips/%/Platform, $(platforms))

	select ARCH_MIGHT_HAVE_PC_PARPORT

	select ARCH_MIGHT_HAVE_PC_SERIO

	select ARCH_USE_CMPXCHG_LOCKREF if 64BIT

	select ARCH_USE_BUILTIN_BSWAP

	select HAVE_CONTEXT_TRACKING

	select HAVE_GENERIC_DMA_COHERENT

	select HAVE_IDE

	select SYSCTL_EXCEPTION_TRACE

	select HAVE_VIRT_CPU_ACCOUNTING_GEN

	select HAVE_IRQ_TIME_ACCOUNTING

	select GENERIC_TIME_VSYSCALL

	select ARCH_CLOCKSOURCE_DATA

menu "Machine selection"

	help

	  This enables support for the IMG Pistachio SoC platform.

config MACH_XILFPGA

	bool "MIPSfpga Xilinx based boards"

	select ARCH_REQUIRE_GPIOLIB

	select BOOT_ELF32

	select BOOT_RAW

	select BUILTIN_DTB

	select CEVT_R4K

	select COMMON_CLK

	select CSRC_R4K

	select IRQ_MIPS_CPU

	select LIBFDT

	select MIPS_CPU_SCACHE

	select SYS_HAS_EARLY_PRINTK

	select SYS_HAS_CPU_MIPS32_R2

	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_LITTLE_ENDIAN

	select SYS_SUPPORTS_ZBOOT_UART16550

	select USE_OF

	select USE_GENERIC_EARLY_PRINTK_8250

	help

	  This enables support for the IMG University Program MIPSfpga platform.

config MIPS_MALTA

	bool "MIPS Malta board"

	select ARCH_MAY_HAVE_PC_FDC

	select MIPS_L1_CACHE_SHIFT_6

	select PCI_GT64XXX_PCI0

	select MIPS_MSC

	select SMP_UP if SMP

	select SWAP_IO_SPACE

	select SYS_HAS_CPU_MIPS32_R1

	select SYS_HAS_CPU_MIPS32_R2

	select SYS_SUPPORTS_ZBOOT

	select USE_OF

	select ZONE_DMA32 if 64BIT

	select BUILTIN_DTB

	select LIBFDT

	help

	  This enables support for the MIPS Technologies Malta evaluation

	  board.

source "arch/mips/loongson64/Kconfig"

source "arch/mips/netlogic/Kconfig"

source "arch/mips/paravirt/Kconfig"

source "arch/mips/xilfpga/Kconfig"

endmenu

config CSRC_SB1250

	bool

config MIPS_CLOCK_VSYSCALL

	def_bool CSRC_R4K || CLKSRC_MIPS_GIC

config GPIO_TXX9

	select ARCH_REQUIRE_GPIOLIB

	bool

	help

	 Allows the configuration of the timer frequency.

	config HZ_24

		bool "24 HZ" if SYS_SUPPORTS_24HZ || SYS_SUPPORTS_ARBIT_HZ

	config HZ_48

		bool "48 HZ" if SYS_SUPPORTS_48HZ || SYS_SUPPORTS_ARBIT_HZ

endchoice

config SYS_SUPPORTS_24HZ

	bool

config SYS_SUPPORTS_48HZ

	bool

config SYS_SUPPORTS_ARBIT_HZ

	bool

	default y if !SYS_SUPPORTS_48HZ && !SYS_SUPPORTS_100HZ && \

		     !SYS_SUPPORTS_128HZ && !SYS_SUPPORTS_250HZ && \

		     !SYS_SUPPORTS_256HZ && !SYS_SUPPORTS_1000HZ && \

	default y if !SYS_SUPPORTS_24HZ && \

		     !SYS_SUPPORTS_48HZ && \

		     !SYS_SUPPORTS_100HZ && \

		     !SYS_SUPPORTS_128HZ && \

		     !SYS_SUPPORTS_250HZ && \

		     !SYS_SUPPORTS_256HZ && \

		     !SYS_SUPPORTS_1000HZ && \

		     !SYS_SUPPORTS_1024HZ

config HZ

	int

	default 24 if HZ_24

	default 48 if HZ_48

	default 100 if HZ_100

	default 128 if HZ_128

	bool

choice

	prompt "Kernel appended dtb support" if OF

	prompt "Kernel appended dtb support" if USE_OF

	default MIPS_NO_APPENDED_DTB

	config MIPS_NO_APPENDED_DTB

		help

		  Do not enable appended dtb support.

	config MIPS_ELF_APPENDED_DTB

		bool "vmlinux"

		help

		  With this option, the boot code will look for a device tree binary

		  DTB) included in the vmlinux ELF section .appended_dtb. By default

		  it is empty and the DTB can be appended using binutils command

		  objcopy:

		    objcopy --update-section .appended_dtb=<filename>.dtb vmlinux

		  This is meant as a backward compatiblity convenience for those

		  systems with a bootloader that can't be upgraded to accommodate

		  the documented boot protocol using a device tree.

	config MIPS_RAW_APPENDED_DTB

		bool "vmlinux.bin"

		help

		  if you don't intend to always append a DTB.

endchoice

choice

	prompt "Kernel command line type" if !CMDLINE_OVERRIDE

	default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \

					 !MIPS_MALTA && !MIPS_SEAD3 && \

					 !CAVIUM_OCTEON_SOC

	default MIPS_CMDLINE_FROM_BOOTLOADER

	config MIPS_CMDLINE_FROM_DTB

		depends on USE_OF

		bool "Dtb kernel arguments if available"

	config MIPS_CMDLINE_DTB_EXTEND

		depends on USE_OF

		bool "Extend dtb kernel arguments with bootloader arguments"

	config MIPS_CMDLINE_FROM_BOOTLOADER

		bool "Bootloader kernel arguments if available"

endchoice

endmenu

config LOCKDEP_SUPPORT

	bool

	default y

config HAVE_LATENCYTOP_SUPPORT

	bool

	default y

config PGTABLE_LEVELS

	int

	default 3 if 64BIT && !PAGE_SIZE_64KB

	help

	  Add several files to the debugfs to test spinlock speed.

if CPU_MIPSR6

choice

	prompt "Compact branch policy"

	default MIPS_COMPACT_BRANCHES_OPTIMAL

config MIPS_COMPACT_BRANCHES_NEVER

	bool "Never (force delay slot branches)"

	help

	  Pass the -mcompact-branches=never flag to the compiler in order to

	  force it to always emit branches with delay slots, and make no use

	  of the compact branch instructions introduced by MIPSr6. This is

	  useful if you suspect there may be an issue with compact branches in

	  either the compiler or the CPU.

config MIPS_COMPACT_BRANCHES_OPTIMAL

	bool "Optimal (use where beneficial)"

	help

	  Pass the -mcompact-branches=optimal flag to the compiler in order for

	  it to make use of compact branch instructions where it deems them

	  beneficial, and use branches with delay slots elsewhere. This is the

	  default compiler behaviour, and should be used unless you have a

	  reason to choose otherwise.

config MIPS_COMPACT_BRANCHES_ALWAYS

	bool "Always (force compact branches)"

	help

	  Pass the -mcompact-branches=always flag to the compiler in order to

	  force it to always emit compact branches, making no use of branch

	  instructions with delay slots. This can result in more compact code

	  which may be beneficial in some scenarios.

endchoice

endif # CPU_MIPSR6

config SCACHE_DEBUGFS

	bool "L2 cache debugfs entries"

	depends on DEBUG_FS

	help

	  Enable this to allow parts of the L2 cache configuration, such as

	  whether or not prefetching is enabled, to be exposed to userland

	  via debugfs.

	  If unsure, say N.

menuconfig MIPS_CPS_NS16550

	bool "CPS SMP NS16550 UART output"

	depends on MIPS_CPS

	help

	  Output debug information via an ns16550 compatible UART if exceptions

	  occur early in the boot process of a secondary core.

if MIPS_CPS_NS16550

config MIPS_CPS_NS16550_BASE

	hex "UART Base Address"

	default 0x1b0003f8 if MIPS_MALTA

	help

	  The base address of the ns16550 compatible UART on which to output

	  debug information from the early stages of core startup.

config MIPS_CPS_NS16550_SHIFT

	int "UART Register Shift"

	default 0 if MIPS_MALTA

	help

	  The number of bits to shift ns16550 register indices by in order to

	  form their addresses. That is, log base 2 of the span between

	  adjacent ns16550 registers in the system.

endif # MIPS_CPS_NS16550

endmenu