r8169: shuffle some registers handling around (8168 operation only) (b8363901) · Commits · 戴 / test

I can not argue strongly for (or against) a specific ordering on a purely technical ground but the patch avoids to swallow Realtek's changes in one big, hard-to-read gulp. Let aside the way the RxConfig register is written (see rtl_set_rx_tx_config_registers / RxConfig / rtl_set_rx_mode), this change brings the registers write ordering closer with Realtek's driver one (version 8.006.00) for the 8168 chipsets. More 8168 specific code which touches the Configx registers will be added in the section covered by Cfg9346_UnLock / Cfg9346_Lock. This code should not be the cause of regression for 810x and 8110 users. Signed-off-by:

Francois Romieu <romieu@fr.zoreil.com> Cc: Edward Hsu <edward_hsu@realtek.com.tw>

drivers/net/r8169.c

+7 −6

Original line number	Diff line number	Diff line
		@@ -2396,14 +2396,10 @@ static void rtl_hw_start_8168(struct net_device *dev)

		rtl_set_rx_max_size(ioaddr);

		rtl_set_rx_tx_config_registers(tp);

		tp->cp_cmd \|= RTL_R16(CPlusCmd) \| PktCntrDisable \| INTT_1;

		RTL_W16(CPlusCmd, tp->cp_cmd);

		rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);

		RTL_W16(IntrMitigate, 0x5151);

		/* Work around for RxFIFO overflow. */
		@@ -2414,14 +2410,19 @@ static void rtl_hw_start_8168(struct net_device *dev)

		rtl_set_rx_tx_desc_registers(tp, ioaddr);

		RTL_W8(Cfg9346, Cfg9346_Lock);
		rtl_set_rx_mode(dev);

		RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) \|
		(InterFrameGap << TxInterFrameGapShift));

		RTL_R8(IntrMask);

		rtl_set_rx_mode(dev);
		rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);

		RTL_W8(ChipCmd, CmdTxEnb \| CmdRxEnb);

		RTL_W8(Cfg9346, Cfg9346_Lock);

		RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);

		RTL_W16(IntrMask, tp->intr_event);

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