Commit b82ffb33 authored by Dave Gerlach's avatar Dave Gerlach Committed by Tony Lindgren
Browse files

ARM: dts: dra7: Move cpus node to parent dts for dra74x and dra72x 



Nearly all of the information in the cpus node, especially for cpu0, is
the same between dra74x and dra72x so move the common information to
the parent dra7.dtsi to avoid duplication of data.

Signed-off-by: default avatarDave Gerlach <d-gerlach@ti.com>
Acked-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 62e4feed

arch/arm/boot/dts/dra7.dtsi

+27 −0
Original line number Diff line number Diff line
@@ -73,6 +73,33 @@ 
		interrupt-parent = <&gic>;

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a15";

			reg = <0>;



			operating-points = <

				/* kHz    uV */

				1000000	1060000

				1176000	1160000

				>;



			clocks = <&dpll_mpu_ck>;

			clock-names = "cpu";



			clock-latency = <300000>; /* From omap-cpufreq driver */



			/* cooling options */

			cooling-min-level = <0>;

			cooling-max-level = <2>;

			#cooling-cells = <2>; /* min followed by max */

		};

	};



	/*

	 * The soc node represents the soc top level view. It is used for IPs

	 * that are not memory mapped in the MPU view or for the MPU itself.

arch/arm/boot/dts/dra72x.dtsi

+0 −16
Original line number Diff line number Diff line
@@ -12,22 +12,6 @@ 
/ {

	compatible = "ti,dra722", "ti,dra72", "ti,dra7";



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a15";

			reg = <0>;



			/* cooling options */

			cooling-min-level = <0>;

			cooling-max-level = <2>;

			#cooling-cells = <2>; /* min followed by max */

		};

	};



	pmu {

		compatible = "arm,cortex-a15-pmu";

		interrupt-parent = <&wakeupgen>;

arch/arm/boot/dts/dra74x.dtsi

+0 −24
Original line number Diff line number Diff line
@@ -13,30 +13,6 @@ 
	compatible = "ti,dra742", "ti,dra74", "ti,dra7";



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a15";

			reg = <0>;



			operating-points = <

				/* kHz    uV */

				1000000	1060000

				1176000	1160000

				>;



			clocks = <&dpll_mpu_ck>;

			clock-names = "cpu";



			clock-latency = <300000>; /* From omap-cpufreq driver */



			/* cooling options */

			cooling-min-level = <0>;

			cooling-max-level = <2>;

			#cooling-cells = <2>; /* min followed by max */

		};

		cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a15";

CRA Git | Maintained and supported by SUSTech CRA and CCSE