Commit b81a6179 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2016-09-19' of git://anongit.freedesktop.org/drm-intel into drm-next 

- refactor the sseu code (Imre)
- refine guc dmesg output (Dave Gordon)
- more vgpu work
- more skl wm fixes (Lyude)
- refactor dpll code in prep for upfront link training (Jim Bride et al)
- consolidate all platform feature checks into intel_device_info (Carlos Santa)
- refactor elsp/execlist submission as prep for re-submission after hang
  recovery and eventually scheduling (Chris Wilson)
- allow synchronous gpu reset handling, to remove tricky/impossible/fragile
  error recovery code (Chris Wilson)
- prep work for nonblocking (execlist) submission, using fences to track
  depencies and drive elsp submission (Chris Wilson)
- partial error recover/resubmission of non-guilty batches after hangs (Chris Wilson)
- full dma-buf implicit fencing support (Chris Wilson)
- dp link training fixes (Jim, Dhinkaran, Navare, ...)
- obey dp branch device pixel rate/bpc/clock limits (Mika Kahola), needed for
  many vga dongles
- bunch of small cleanups and polish all over, as usual

[airlied: printing macros collided]

* tag 'drm-intel-next-2016-09-19' of git://anongit.freedesktop.org/drm-intel: (163 commits)
  drm/i915: Update DRIVER_DATE to 20160919
  drm: Fix DisplayPort branch device ID kernel-doc
  drm/i915: use NULL for NULL pointers
  drm/i915: do not use 'false' as a NULL pointer
  drm/i915: make intel_dp_compute_bpp static
  drm: Add DP branch device info on debugfs
  drm/i915: Update bits per component for display info
  drm/i915: Check pixel rate for DP to VGA dongle
  drm/i915: Read DP branch device SW revision
  drm/i915: Read DP branch device HW revision
  drm/i915: Cleanup DisplayPort AUX channel initialization
  drm: Read DP branch device id
  drm: Helper to read max bits per component
  drm: Helper to read max clock rate
  drm: Drop VGA from bpc definitions
  drm: Add missing DP downstream port types
  drm/i915: Add ddb size field to device info structure
  drm/i915/guc: general tidying up (submission)
  drm/i915/guc: general tidying up (loader)
  drm/i915: clarify PMINTRMSK/pm_intr_keep usage
  ...
parents bd4a68da 6e05f3d3

arch/x86/kernel/early-quirks.c

+3 −6
Original line number Diff line number Diff line
@@ -507,8 +507,7 @@ static const struct pci_device_id intel_early_ids[] __initconst = { 
	INTEL_I915GM_IDS(&gen3_early_ops),

	INTEL_I945G_IDS(&gen3_early_ops),

	INTEL_I945GM_IDS(&gen3_early_ops),

	INTEL_VLV_M_IDS(&gen6_early_ops),

	INTEL_VLV_D_IDS(&gen6_early_ops),

	INTEL_VLV_IDS(&gen6_early_ops),

	INTEL_PINEVIEW_IDS(&gen3_early_ops),

	INTEL_I965G_IDS(&gen3_early_ops),

	INTEL_G33_IDS(&gen3_early_ops),
@@ -521,10 +520,8 @@ static const struct pci_device_id intel_early_ids[] __initconst = { 
	INTEL_SNB_M_IDS(&gen6_early_ops),

	INTEL_IVB_M_IDS(&gen6_early_ops),

	INTEL_IVB_D_IDS(&gen6_early_ops),

	INTEL_HSW_D_IDS(&gen6_early_ops),

	INTEL_HSW_M_IDS(&gen6_early_ops),

	INTEL_BDW_M_IDS(&gen8_early_ops),

	INTEL_BDW_D_IDS(&gen8_early_ops),

	INTEL_HSW_IDS(&gen6_early_ops),

	INTEL_BDW_IDS(&gen8_early_ops),

	INTEL_CHV_IDS(&chv_early_ops),

	INTEL_SKL_IDS(&gen9_early_ops),

	INTEL_BXT_IDS(&gen9_early_ops),

drivers/gpu/drm/drm_dp_helper.c

+173 −0
Original line number Diff line number Diff line
@@ -439,6 +439,179 @@ int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link) 
}

EXPORT_SYMBOL(drm_dp_link_configure);



/**

 * drm_dp_downstream_max_clock() - extract branch device max

 *                                 pixel rate for legacy VGA

 *                                 converter or max TMDS clock

 *                                 rate for others

 * @dpcd: DisplayPort configuration data

 * @port_cap: port capabilities

 *

 * Returns max clock in kHz on success or 0 if max clock not defined

 */

int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

				const u8 port_cap[4])

{

	int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;

	bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &

		DP_DETAILED_CAP_INFO_AVAILABLE;



	if (!detailed_cap_info)

		return 0;



	switch (type) {

	case DP_DS_PORT_TYPE_VGA:

		return port_cap[1] * 8 * 1000;

	case DP_DS_PORT_TYPE_DVI:

	case DP_DS_PORT_TYPE_HDMI:

	case DP_DS_PORT_TYPE_DP_DUALMODE:

		return port_cap[1] * 2500;

	default:

		return 0;

	}

}

EXPORT_SYMBOL(drm_dp_downstream_max_clock);



/**

 * drm_dp_downstream_max_bpc() - extract branch device max

 *                               bits per component

 * @dpcd: DisplayPort configuration data

 * @port_cap: port capabilities

 *

 * Returns max bpc on success or 0 if max bpc not defined

 */

int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

			      const u8 port_cap[4])

{

	int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;

	bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &

		DP_DETAILED_CAP_INFO_AVAILABLE;

	int bpc;



	if (!detailed_cap_info)

		return 0;



	switch (type) {

	case DP_DS_PORT_TYPE_VGA:

	case DP_DS_PORT_TYPE_DVI:

	case DP_DS_PORT_TYPE_HDMI:

	case DP_DS_PORT_TYPE_DP_DUALMODE:

		bpc = port_cap[2] & DP_DS_MAX_BPC_MASK;



		switch (bpc) {

		case DP_DS_8BPC:

			return 8;

		case DP_DS_10BPC:

			return 10;

		case DP_DS_12BPC:

			return 12;

		case DP_DS_16BPC:

			return 16;

		}

	default:

		return 0;

	}

}

EXPORT_SYMBOL(drm_dp_downstream_max_bpc);



/**

 * drm_dp_downstream_id() - identify branch device

 * @aux: DisplayPort AUX channel

 * @id: DisplayPort branch device id

 *

 * Returns branch device id on success or NULL on failure

 */

int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6])

{

	return drm_dp_dpcd_read(aux, DP_BRANCH_ID, id, 6);

}

EXPORT_SYMBOL(drm_dp_downstream_id);



/**

 * drm_dp_downstream_debug() - debug DP branch devices

 * @m: pointer for debugfs file

 * @dpcd: DisplayPort configuration data

 * @port_cap: port capabilities

 * @aux: DisplayPort AUX channel

 *

 */

void drm_dp_downstream_debug(struct seq_file *m,

			     const u8 dpcd[DP_RECEIVER_CAP_SIZE],

			     const u8 port_cap[4], struct drm_dp_aux *aux)

{

	bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &

				 DP_DETAILED_CAP_INFO_AVAILABLE;

	int clk;

	int bpc;

	char id[6];

	int len;

	uint8_t rev[2];

	int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;

	bool branch_device = dpcd[DP_DOWNSTREAMPORT_PRESENT] &

			     DP_DWN_STRM_PORT_PRESENT;



	seq_printf(m, "\tDP branch device present: %s\n",

		   branch_device ? "yes" : "no");



	if (!branch_device)

		return;



	switch (type) {

	case DP_DS_PORT_TYPE_DP:

		seq_puts(m, "\t\tType: DisplayPort\n");

		break;

	case DP_DS_PORT_TYPE_VGA:

		seq_puts(m, "\t\tType: VGA\n");

		break;

	case DP_DS_PORT_TYPE_DVI:

		seq_puts(m, "\t\tType: DVI\n");

		break;

	case DP_DS_PORT_TYPE_HDMI:

		seq_puts(m, "\t\tType: HDMI\n");

		break;

	case DP_DS_PORT_TYPE_NON_EDID:

		seq_puts(m, "\t\tType: others without EDID support\n");

		break;

	case DP_DS_PORT_TYPE_DP_DUALMODE:

		seq_puts(m, "\t\tType: DP++\n");

		break;

	case DP_DS_PORT_TYPE_WIRELESS:

		seq_puts(m, "\t\tType: Wireless\n");

		break;

	default:

		seq_puts(m, "\t\tType: N/A\n");

	}



	drm_dp_downstream_id(aux, id);

	seq_printf(m, "\t\tID: %s\n", id);



	len = drm_dp_dpcd_read(aux, DP_BRANCH_HW_REV, &rev[0], 1);

	if (len > 0)

		seq_printf(m, "\t\tHW: %d.%d\n",

			   (rev[0] & 0xf0) >> 4, rev[0] & 0xf);



	len = drm_dp_dpcd_read(aux, DP_BRANCH_SW_REV, &rev, 2);

	if (len > 0)

		seq_printf(m, "\t\tSW: %d.%d\n", rev[0], rev[1]);



	if (detailed_cap_info) {

		clk = drm_dp_downstream_max_clock(dpcd, port_cap);



		if (clk > 0) {

			if (type == DP_DS_PORT_TYPE_VGA)

				seq_printf(m, "\t\tMax dot clock: %d kHz\n", clk);

			else

				seq_printf(m, "\t\tMax TMDS clock: %d kHz\n", clk);

		}



		bpc = drm_dp_downstream_max_bpc(dpcd, port_cap);



		if (bpc > 0)

			seq_printf(m, "\t\tMax bpc: %d\n", bpc);

	}

}

EXPORT_SYMBOL(drm_dp_downstream_debug);



/*

 * I2C-over-AUX implementation

 */

drivers/gpu/drm/i915/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ i915-y := i915_drv.o \ 
	  i915_params.o \

	  i915_pci.o \

          i915_suspend.o \

	  i915_sw_fence.o \

	  i915_sysfs.o \

	  intel_csr.o \

	  intel_device_info.o \

drivers/gpu/drm/i915/i915_cmd_parser.c

+1 −1
Original line number Diff line number Diff line
@@ -984,7 +984,7 @@ static u32 *copy_batch(struct drm_i915_gem_object *dst_obj, 


	src = ERR_PTR(-ENODEV);

	if (src_needs_clflush &&

	    i915_memcpy_from_wc((void *)(uintptr_t)batch_start_offset, 0, 0)) {

	    i915_memcpy_from_wc((void *)(uintptr_t)batch_start_offset, NULL, 0)) {

		src = i915_gem_object_pin_map(src_obj, I915_MAP_WC);

		if (!IS_ERR(src)) {

			i915_memcpy_from_wc(dst,

drivers/gpu/drm/i915/i915_debugfs.c

+480 −535

File changed.

Preview size limit exceeded, changes collapsed.

CRA Git | Maintained and supported by SUSTech CRA and CCSE