Commit b7f7a0b5 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'reset-for-v5.5' of git://git.pengutronix.de/git/pza/linux into arm/drivers

Reset controller updates for v5.5

This tag adds support for Meson SM1 ARB resets, Uniphier Pro5 USB3
resets, the Meson-A1 reset controller, SocFPGA Agilex resets, and
Realtek RTD1195/RTD1295 resets.
It adds some reset controller API keywords for get_maintainers.pl and
makes a few remaining reset_control_ops const. Also included are
a conversion of the Qualcomm device tree bindings to yaml and a few
small kerneldoc improvements.

* tag 'reset-for-v5.5' of git://git.pengutronix.de/git/pza/linux:
  reset: document (devm_)reset_control_get_optional variants
  reset: improve of_xlate documentation
  reset: simple: Add Realtek RTD1195/RTD1295
  reset: simple: Keep alphabetical order
  MAINTAINERS: add reset controller framework keywords
  reset: zynqmp: Make reset_control_ops const
  reset: hisilicon: hi3660: Make reset_control_ops const
  reset: build simple reset controller driver for Agilex
  reset: add support for the Meson-A1 SoC Reset Controller
  dt-bindings: reset: add bindings for the Meson-A1 SoC Reset Controller
  reset: uniphier-glue: Add Pro5 USB3 support
  dt-bindings: reset: pdc: Convert PDC Global bindings to yaml
  dt-bindings: reset: aoss: Convert AOSS reset bindings to yaml
  reset: Remove copy'n'paste redundancy in the comments
  reset: meson-audio-arb: add sm1 support
  reset: dt-bindings: meson: update arb bindings for sm1

Link: https://lore.kernel.org/r/ede6874508472d0917dca770ef80b90626b0f205.camel@pengutronix.de


Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 3c1aa0c0 c2ffa00a
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@@ -4,7 +4,8 @@ The Amlogic Audio ARB is a simple device which enables or
disables the access of Audio FIFOs to DDR on AXG based SoC.

Required properties:
- compatible: 'amlogic,meson-axg-audio-arb'
- compatible: 'amlogic,meson-axg-audio-arb' or
	      'amlogic,meson-sm1-audio-arb'
- reg: physical base address of the controller and length of memory
       mapped region.
- clocks: phandle to the fifo peripheral clock provided by the audio
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@@ -16,6 +16,7 @@ properties:
      - amlogic,meson8b-reset # Reset Controller on Meson8b and compatible SoCs
      - amlogic,meson-gxbb-reset # Reset Controller on GXBB and compatible SoCs
      - amlogic,meson-axg-reset # Reset Controller on AXG and compatible SoCs
      - amlogic,meson-a1-reset # Reset Controller on A1 and compatible SoCs

  reg:
    maxItems: 1
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Qualcomm AOSS Reset Controller
======================================

This binding describes a reset-controller found on AOSS-CC (always on subsystem)
for Qualcomm SDM845 SoCs.

Required properties:
- compatible:
	Usage: required
	Value type: <string>
	Definition: must be:
		    "qcom,sdm845-aoss-cc"

- reg:
	Usage: required
	Value type: <prop-encoded-array>
	Definition: must specify the base address and size of the register
	            space.

- #reset-cells:
	Usage: required
	Value type: <uint>
	Definition: must be 1; cell entry represents the reset index.

Example:

aoss_reset: reset-controller@c2a0000 {
	compatible = "qcom,sdm845-aoss-cc";
	reg = <0xc2a0000 0x31000>;
	#reset-cells = <1>;
};

Specifying reset lines connected to IP modules
==============================================

Device nodes that need access to reset lines should
specify them as a reset phandle in their corresponding node as
specified in reset.txt.

For list of all valid reset indicies see
<dt-bindings/reset/qcom,sdm845-aoss.h>

Example:

modem-pil@4080000 {
	...

	resets = <&aoss_reset AOSS_CC_MSS_RESTART>;
	reset-names = "mss_restart";

	...
};
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/reset/qcom,aoss-reset.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm AOSS Reset Controller

maintainers:
  - Sibi Sankar <sibis@codeaurora.org>

description:
  The bindings describe the reset-controller found on AOSS-CC (always on
  subsystem) for Qualcomm Technologies Inc SoCs.

properties:
  compatible:
    oneOf:
      - description: on SC7180 SoCs the following compatibles must be specified
        items:
          - const: "qcom,sc7180-aoss-cc"
          - const: "qcom,sdm845-aoss-cc"

      - description: on SDM845 SoCs the following compatibles must be specified
        items:
          - const: "qcom,sdm845-aoss-cc"

  reg:
    maxItems: 1

  '#reset-cells':
    const: 1

required:
  - compatible
  - reg
  - '#reset-cells'

additionalProperties: false

examples:
  - |
    aoss_reset: reset-controller@c2a0000 {
      compatible = "qcom,sdm845-aoss-cc";
      reg = <0xc2a0000 0x31000>;
      #reset-cells = <1>;
    };
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PDC Global
======================================

This binding describes a reset-controller found on PDC-Global (Power Domain
Controller) block for Qualcomm Technologies Inc SDM845 SoCs.

Required properties:
- compatible:
	Usage: required
	Value type: <string>
	Definition: must be:
		    "qcom,sdm845-pdc-global"

- reg:
	Usage: required
	Value type: <prop-encoded-array>
	Definition: must specify the base address and size of the register
	            space.

- #reset-cells:
	Usage: required
	Value type: <uint>
	Definition: must be 1; cell entry represents the reset index.

Example:

pdc_reset: reset-controller@b2e0000 {
	compatible = "qcom,sdm845-pdc-global";
	reg = <0xb2e0000 0x20000>;
	#reset-cells = <1>;
};

PDC reset clients
======================================

Device nodes that need access to reset lines should
specify them as a reset phandle in their corresponding node as
specified in reset.txt.

For a list of all valid reset indices see
<dt-bindings/reset/qcom,sdm845-pdc.h>

Example:

modem-pil@4080000 {
	...

	resets = <&pdc_reset PDC_MODEM_SYNC_RESET>;
	reset-names = "pdc_reset";

	...
};
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