Commit b7a2bc18 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/imem: convert to new-style nvkm_subdev 



Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 8de65bd0

drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h

+10 −25
Original line number Diff line number Diff line
@@ -4,14 +4,11 @@ 
struct nvkm_memory;



struct nvkm_instmem {

	const struct nvkm_instmem_func *func;

	struct nvkm_subdev subdev;

	struct list_head list;



	struct list_head list;

	u32 reserved;

	int (*alloc)(struct nvkm_instmem *, u32 size, u32 align, bool zero,

		     struct nvkm_memory **);



	const struct nvkm_instmem_func *func;



	struct nvkm_memory *vbios;

	struct nvkm_ramht  *ramht;
@@ -19,26 +16,14 @@ struct nvkm_instmem { 
	struct nvkm_memory *ramfc;

};



struct nvkm_instmem_func {

	u32  (*rd32)(struct nvkm_instmem *, u32 addr);

	void (*wr32)(struct nvkm_instmem *, u32 addr, u32 data);

};



static inline struct nvkm_instmem *

nvkm_instmem(void *obj)

{

	/* nv04/nv40 impls need to create objects in their constructor,

	 * which is before the subdev pointer is valid

	 */

	if (nv_iclass(obj, NV_SUBDEV_CLASS) &&

	    nv_subidx(obj) == NVDEV_SUBDEV_INSTMEM)

		return obj;

u32 nvkm_instmem_rd32(struct nvkm_instmem *, u32 addr);

void nvkm_instmem_wr32(struct nvkm_instmem *, u32 addr, u32 data);

int nvkm_instobj_new(struct nvkm_instmem *, u32 size, u32 align, bool zero,

		     struct nvkm_memory **);



	return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_INSTMEM);

}



extern struct nvkm_oclass *nv04_instmem_oclass;

extern struct nvkm_oclass *nv40_instmem_oclass;

extern struct nvkm_oclass *nv50_instmem_oclass;

extern struct nvkm_oclass *gk20a_instmem_oclass;

int nv04_instmem_new(struct nvkm_device *, int, struct nvkm_instmem **);

int nv40_instmem_new(struct nvkm_device *, int, struct nvkm_instmem **);

int nv50_instmem_new(struct nvkm_device *, int, struct nvkm_instmem **);

int gk20a_instmem_new(struct nvkm_device *, int, struct nvkm_instmem **);

#endif

drivers/gpu/drm/nouveau/nvkm/core/memory.c

+1 −1
Original line number Diff line number Diff line
@@ -55,7 +55,7 @@ nvkm_memory_new(struct nvkm_device *device, enum nvkm_memory_target target, 
	if (unlikely(target != NVKM_MEM_TARGET_INST || !imem))

		return -ENOSYS;



	ret = imem->alloc(imem, size, align, zero, &memory);

	ret = nvkm_instobj_new(imem, size, align, zero, &memory);

	if (ret)

		return ret;

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

+69 −69
Original line number Diff line number Diff line
@@ -82,7 +82,7 @@ nv4_chipset = { 
	.devinit = nv04_devinit_new,

	.fb = nv04_fb_new,

	.i2c = nv04_i2c_new,

//	.imem = nv04_instmem_new,

	.imem = nv04_instmem_new,

//	.mc = nv04_mc_new,

//	.mmu = nv04_mmu_new,

//	.timer = nv04_timer_new,
@@ -102,7 +102,7 @@ nv5_chipset = { 
	.devinit = nv05_devinit_new,

	.fb = nv04_fb_new,

	.i2c = nv04_i2c_new,

//	.imem = nv04_instmem_new,

	.imem = nv04_instmem_new,

//	.mc = nv04_mc_new,

//	.mmu = nv04_mmu_new,

//	.timer = nv04_timer_new,
@@ -123,7 +123,7 @@ nv10_chipset = { 
	.fb = nv10_fb_new,

	.gpio = nv10_gpio_new,

	.i2c = nv04_i2c_new,

//	.imem = nv04_instmem_new,

	.imem = nv04_instmem_new,

//	.mc = nv04_mc_new,

//	.mmu = nv04_mmu_new,

//	.timer = nv04_timer_new,
@@ -142,7 +142,7 @@ nv11_chipset = { 
	.fb = nv10_fb_new,

	.gpio = nv10_gpio_new,

	.i2c = nv04_i2c_new,

//	.imem = nv04_instmem_new,

	.imem = nv04_instmem_new,

//	.mc = nv04_mc_new,

//	.mmu = nv04_mmu_new,

//	.timer = nv04_timer_new,
@@ -163,7 +163,7 @@ nv15_chipset = { 
	.fb = nv10_fb_new,

	.gpio = nv10_gpio_new,

	.i2c = nv04_i2c_new,

//	.imem = nv04_instmem_new,

	.imem = nv04_instmem_new,

//	.mc = nv04_mc_new,

//	.mmu = nv04_mmu_new,

//	.timer = nv04_timer_new,
@@ -184,7 +184,7 @@ nv17_chipset = { 
	.fb = nv10_fb_new,

	.gpio = nv10_gpio_new,

	.i2c = nv04_i2c_new,

//	.imem = nv04_instmem_new,

	.imem = nv04_instmem_new,

//	.mc = nv04_mc_new,

//	.mmu = nv04_mmu_new,

//	.timer = nv04_timer_new,
@@ -205,7 +205,7 @@ nv18_chipset = { 
	.fb = nv10_fb_new,

	.gpio = nv10_gpio_new,

	.i2c = nv04_i2c_new,

//	.imem = nv04_instmem_new,

	.imem = nv04_instmem_new,

//	.mc = nv04_mc_new,

//	.mmu = nv04_mmu_new,

//	.timer = nv04_timer_new,
@@ -226,7 +226,7 @@ nv1a_chipset = { 
	.fb = nv1a_fb_new,

	.gpio = nv10_gpio_new,

	.i2c = nv04_i2c_new,

//	.imem = nv04_instmem_new,

	.imem = nv04_instmem_new,

//	.mc = nv04_mc_new,

//	.mmu = nv04_mmu_new,

//	.timer = nv04_timer_new,
@@ -247,7 +247,7 @@ nv1f_chipset = { 
	.fb = nv1a_fb_new,

	.gpio = nv10_gpio_new,

	.i2c = nv04_i2c_new,

//	.imem = nv04_instmem_new,

	.imem = nv04_instmem_new,

//	.mc = nv04_mc_new,

//	.mmu = nv04_mmu_new,

//	.timer = nv04_timer_new,
@@ -268,7 +268,7 @@ nv20_chipset = { 
	.fb = nv20_fb_new,

	.gpio = nv10_gpio_new,

	.i2c = nv04_i2c_new,

//	.imem = nv04_instmem_new,

	.imem = nv04_instmem_new,

//	.mc = nv04_mc_new,

//	.mmu = nv04_mmu_new,

//	.timer = nv04_timer_new,
@@ -289,7 +289,7 @@ nv25_chipset = { 
	.fb = nv25_fb_new,

	.gpio = nv10_gpio_new,

	.i2c = nv04_i2c_new,

//	.imem = nv04_instmem_new,

	.imem = nv04_instmem_new,

//	.mc = nv04_mc_new,

//	.mmu = nv04_mmu_new,

//	.timer = nv04_timer_new,
@@ -310,7 +310,7 @@ nv28_chipset = { 
	.fb = nv25_fb_new,

	.gpio = nv10_gpio_new,

	.i2c = nv04_i2c_new,

//	.imem = nv04_instmem_new,

	.imem = nv04_instmem_new,

//	.mc = nv04_mc_new,

//	.mmu = nv04_mmu_new,

//	.timer = nv04_timer_new,
@@ -331,7 +331,7 @@ nv2a_chipset = { 
	.fb = nv25_fb_new,

	.gpio = nv10_gpio_new,

	.i2c = nv04_i2c_new,

//	.imem = nv04_instmem_new,

	.imem = nv04_instmem_new,

//	.mc = nv04_mc_new,

//	.mmu = nv04_mmu_new,

//	.timer = nv04_timer_new,
@@ -352,7 +352,7 @@ nv30_chipset = { 
	.fb = nv30_fb_new,

	.gpio = nv10_gpio_new,

	.i2c = nv04_i2c_new,

//	.imem = nv04_instmem_new,

	.imem = nv04_instmem_new,

//	.mc = nv04_mc_new,

//	.mmu = nv04_mmu_new,

//	.timer = nv04_timer_new,
@@ -373,7 +373,7 @@ nv31_chipset = { 
	.fb = nv30_fb_new,

	.gpio = nv10_gpio_new,

	.i2c = nv04_i2c_new,

//	.imem = nv04_instmem_new,

	.imem = nv04_instmem_new,

//	.mc = nv04_mc_new,

//	.mmu = nv04_mmu_new,

//	.timer = nv04_timer_new,
@@ -395,7 +395,7 @@ nv34_chipset = { 
	.fb = nv10_fb_new,

	.gpio = nv10_gpio_new,

	.i2c = nv04_i2c_new,

//	.imem = nv04_instmem_new,

	.imem = nv04_instmem_new,

//	.mc = nv04_mc_new,

//	.mmu = nv04_mmu_new,

//	.timer = nv04_timer_new,
@@ -417,7 +417,7 @@ nv35_chipset = { 
	.fb = nv35_fb_new,

	.gpio = nv10_gpio_new,

	.i2c = nv04_i2c_new,

//	.imem = nv04_instmem_new,

	.imem = nv04_instmem_new,

//	.mc = nv04_mc_new,

//	.mmu = nv04_mmu_new,

//	.timer = nv04_timer_new,
@@ -438,7 +438,7 @@ nv36_chipset = { 
	.fb = nv36_fb_new,

	.gpio = nv10_gpio_new,

	.i2c = nv04_i2c_new,

//	.imem = nv04_instmem_new,

	.imem = nv04_instmem_new,

//	.mc = nv04_mc_new,

//	.mmu = nv04_mmu_new,

//	.timer = nv04_timer_new,
@@ -460,7 +460,7 @@ nv40_chipset = { 
	.fb = nv40_fb_new,

	.gpio = nv10_gpio_new,

	.i2c = nv04_i2c_new,

//	.imem = nv40_instmem_new,

	.imem = nv40_instmem_new,

//	.mc = nv40_mc_new,

//	.mmu = nv04_mmu_new,

//	.therm = nv40_therm_new,
@@ -485,7 +485,7 @@ nv41_chipset = { 
	.fb = nv41_fb_new,

	.gpio = nv10_gpio_new,

	.i2c = nv04_i2c_new,

//	.imem = nv40_instmem_new,

	.imem = nv40_instmem_new,

//	.mc = nv40_mc_new,

//	.mmu = nv41_mmu_new,

//	.therm = nv40_therm_new,
@@ -510,7 +510,7 @@ nv42_chipset = { 
	.fb = nv41_fb_new,

	.gpio = nv10_gpio_new,

	.i2c = nv04_i2c_new,

//	.imem = nv40_instmem_new,

	.imem = nv40_instmem_new,

//	.mc = nv40_mc_new,

//	.mmu = nv41_mmu_new,

//	.therm = nv40_therm_new,
@@ -535,7 +535,7 @@ nv43_chipset = { 
	.fb = nv41_fb_new,

	.gpio = nv10_gpio_new,

	.i2c = nv04_i2c_new,

//	.imem = nv40_instmem_new,

	.imem = nv40_instmem_new,

//	.mc = nv40_mc_new,

//	.mmu = nv41_mmu_new,

//	.therm = nv40_therm_new,
@@ -560,7 +560,7 @@ nv44_chipset = { 
	.fb = nv44_fb_new,

	.gpio = nv10_gpio_new,

	.i2c = nv04_i2c_new,

//	.imem = nv40_instmem_new,

	.imem = nv40_instmem_new,

//	.mc = nv44_mc_new,

//	.mmu = nv44_mmu_new,

//	.therm = nv40_therm_new,
@@ -585,7 +585,7 @@ nv45_chipset = { 
	.fb = nv40_fb_new,

	.gpio = nv10_gpio_new,

	.i2c = nv04_i2c_new,

//	.imem = nv40_instmem_new,

	.imem = nv40_instmem_new,

//	.mc = nv40_mc_new,

//	.mmu = nv04_mmu_new,

//	.therm = nv40_therm_new,
@@ -610,7 +610,7 @@ nv46_chipset = { 
	.fb = nv46_fb_new,

	.gpio = nv10_gpio_new,

	.i2c = nv04_i2c_new,

//	.imem = nv40_instmem_new,

	.imem = nv40_instmem_new,

//	.mc = nv44_mc_new,

//	.mmu = nv44_mmu_new,

//	.therm = nv40_therm_new,
@@ -635,7 +635,7 @@ nv47_chipset = { 
	.fb = nv47_fb_new,

	.gpio = nv10_gpio_new,

	.i2c = nv04_i2c_new,

//	.imem = nv40_instmem_new,

	.imem = nv40_instmem_new,

//	.mc = nv40_mc_new,

//	.mmu = nv41_mmu_new,

//	.therm = nv40_therm_new,
@@ -660,7 +660,7 @@ nv49_chipset = { 
	.fb = nv49_fb_new,

	.gpio = nv10_gpio_new,

	.i2c = nv04_i2c_new,

//	.imem = nv40_instmem_new,

	.imem = nv40_instmem_new,

//	.mc = nv40_mc_new,

//	.mmu = nv41_mmu_new,

//	.therm = nv40_therm_new,
@@ -685,7 +685,7 @@ nv4a_chipset = { 
	.fb = nv44_fb_new,

	.gpio = nv10_gpio_new,

	.i2c = nv04_i2c_new,

//	.imem = nv40_instmem_new,

	.imem = nv40_instmem_new,

//	.mc = nv44_mc_new,

//	.mmu = nv44_mmu_new,

//	.therm = nv40_therm_new,
@@ -710,7 +710,7 @@ nv4b_chipset = { 
	.fb = nv49_fb_new,

	.gpio = nv10_gpio_new,

	.i2c = nv04_i2c_new,

//	.imem = nv40_instmem_new,

	.imem = nv40_instmem_new,

//	.mc = nv40_mc_new,

//	.mmu = nv41_mmu_new,

//	.therm = nv40_therm_new,
@@ -735,7 +735,7 @@ nv4c_chipset = { 
	.fb = nv46_fb_new,

	.gpio = nv10_gpio_new,

	.i2c = nv04_i2c_new,

//	.imem = nv40_instmem_new,

	.imem = nv40_instmem_new,

//	.mc = nv4c_mc_new,

//	.mmu = nv44_mmu_new,

//	.therm = nv40_therm_new,
@@ -760,7 +760,7 @@ nv4e_chipset = { 
	.fb = nv4e_fb_new,

	.gpio = nv10_gpio_new,

	.i2c = nv4e_i2c_new,

//	.imem = nv40_instmem_new,

	.imem = nv40_instmem_new,

//	.mc = nv4c_mc_new,

//	.mmu = nv44_mmu_new,

//	.therm = nv40_therm_new,
@@ -787,7 +787,7 @@ nv50_chipset = { 
	.fuse = nv50_fuse_new,

	.gpio = nv50_gpio_new,

	.i2c = nv50_i2c_new,

//	.imem = nv50_instmem_new,

	.imem = nv50_instmem_new,

//	.mc = nv50_mc_new,

//	.mmu = nv50_mmu_new,

//	.mxm = nv50_mxm_new,
@@ -813,7 +813,7 @@ nv63_chipset = { 
	.fb = nv46_fb_new,

	.gpio = nv10_gpio_new,

	.i2c = nv04_i2c_new,

//	.imem = nv40_instmem_new,

	.imem = nv40_instmem_new,

//	.mc = nv4c_mc_new,

//	.mmu = nv44_mmu_new,

//	.therm = nv40_therm_new,
@@ -838,7 +838,7 @@ nv67_chipset = { 
	.fb = nv46_fb_new,

	.gpio = nv10_gpio_new,

	.i2c = nv04_i2c_new,

//	.imem = nv40_instmem_new,

	.imem = nv40_instmem_new,

//	.mc = nv4c_mc_new,

//	.mmu = nv44_mmu_new,

//	.therm = nv40_therm_new,
@@ -863,7 +863,7 @@ nv68_chipset = { 
	.fb = nv46_fb_new,

	.gpio = nv10_gpio_new,

	.i2c = nv04_i2c_new,

//	.imem = nv40_instmem_new,

	.imem = nv40_instmem_new,

//	.mc = nv4c_mc_new,

//	.mmu = nv44_mmu_new,

//	.therm = nv40_therm_new,
@@ -890,7 +890,7 @@ nv84_chipset = { 
	.fuse = nv50_fuse_new,

	.gpio = nv50_gpio_new,

	.i2c = nv50_i2c_new,

//	.imem = nv50_instmem_new,

	.imem = nv50_instmem_new,

//	.mc = nv50_mc_new,

//	.mmu = nv50_mmu_new,

//	.mxm = nv50_mxm_new,
@@ -921,7 +921,7 @@ nv86_chipset = { 
	.fuse = nv50_fuse_new,

	.gpio = nv50_gpio_new,

	.i2c = nv50_i2c_new,

//	.imem = nv50_instmem_new,

	.imem = nv50_instmem_new,

//	.mc = nv50_mc_new,

//	.mmu = nv50_mmu_new,

//	.mxm = nv50_mxm_new,
@@ -952,7 +952,7 @@ nv92_chipset = { 
	.fuse = nv50_fuse_new,

	.gpio = nv50_gpio_new,

	.i2c = nv50_i2c_new,

//	.imem = nv50_instmem_new,

	.imem = nv50_instmem_new,

//	.mc = nv50_mc_new,

//	.mmu = nv50_mmu_new,

//	.mxm = nv50_mxm_new,
@@ -983,7 +983,7 @@ nv94_chipset = { 
	.fuse = nv50_fuse_new,

	.gpio = g94_gpio_new,

	.i2c = g94_i2c_new,

//	.imem = nv50_instmem_new,

	.imem = nv50_instmem_new,

//	.mc = g94_mc_new,

//	.mmu = nv50_mmu_new,

//	.mxm = nv50_mxm_new,
@@ -1017,7 +1017,7 @@ nv96_chipset = { 
	.bus = g94_bus_new,

//	.timer = nv04_timer_new,

	.fb = g84_fb_new,

//	.imem = nv50_instmem_new,

	.imem = nv50_instmem_new,

//	.mmu = nv50_mmu_new,

	.bar = g84_bar_new,

//	.volt = nv40_volt_new,
@@ -1048,7 +1048,7 @@ nv98_chipset = { 
	.bus = g94_bus_new,

//	.timer = nv04_timer_new,

	.fb = g84_fb_new,

//	.imem = nv50_instmem_new,

	.imem = nv50_instmem_new,

//	.mmu = nv50_mmu_new,

	.bar = g84_bar_new,

//	.volt = nv40_volt_new,
@@ -1076,7 +1076,7 @@ nva0_chipset = { 
	.fuse = nv50_fuse_new,

	.gpio = g94_gpio_new,

	.i2c = nv50_i2c_new,

//	.imem = nv50_instmem_new,

	.imem = nv50_instmem_new,

//	.mc = g98_mc_new,

//	.mmu = nv50_mmu_new,

//	.mxm = nv50_mxm_new,
@@ -1107,7 +1107,7 @@ nva3_chipset = { 
	.fuse = nv50_fuse_new,

	.gpio = g94_gpio_new,

	.i2c = g94_i2c_new,

//	.imem = nv50_instmem_new,

	.imem = nv50_instmem_new,

//	.mc = g98_mc_new,

//	.mmu = nv50_mmu_new,

//	.mxm = nv50_mxm_new,
@@ -1140,7 +1140,7 @@ nva5_chipset = { 
	.fuse = nv50_fuse_new,

	.gpio = g94_gpio_new,

	.i2c = g94_i2c_new,

//	.imem = nv50_instmem_new,

	.imem = nv50_instmem_new,

//	.mc = g98_mc_new,

//	.mmu = nv50_mmu_new,

//	.mxm = nv50_mxm_new,
@@ -1172,7 +1172,7 @@ nva8_chipset = { 
	.fuse = nv50_fuse_new,

	.gpio = g94_gpio_new,

	.i2c = g94_i2c_new,

//	.imem = nv50_instmem_new,

	.imem = nv50_instmem_new,

//	.mc = g98_mc_new,

//	.mmu = nv50_mmu_new,

//	.mxm = nv50_mxm_new,
@@ -1204,7 +1204,7 @@ nvaa_chipset = { 
	.fuse = nv50_fuse_new,

	.gpio = g94_gpio_new,

	.i2c = g94_i2c_new,

//	.imem = nv50_instmem_new,

	.imem = nv50_instmem_new,

//	.mc = g98_mc_new,

//	.mmu = nv50_mmu_new,

//	.mxm = nv50_mxm_new,
@@ -1235,7 +1235,7 @@ nvac_chipset = { 
	.fuse = nv50_fuse_new,

	.gpio = g94_gpio_new,

	.i2c = g94_i2c_new,

//	.imem = nv50_instmem_new,

	.imem = nv50_instmem_new,

//	.mc = g98_mc_new,

//	.mmu = nv50_mmu_new,

//	.mxm = nv50_mxm_new,
@@ -1266,7 +1266,7 @@ nvaf_chipset = { 
	.fuse = nv50_fuse_new,

	.gpio = g94_gpio_new,

	.i2c = g94_i2c_new,

//	.imem = nv50_instmem_new,

	.imem = nv50_instmem_new,

//	.mc = g98_mc_new,

//	.mmu = nv50_mmu_new,

//	.mxm = nv50_mxm_new,
@@ -1299,7 +1299,7 @@ nvc0_chipset = { 
	.gpio = g94_gpio_new,

	.i2c = g94_i2c_new,

	.ibus = gf100_ibus_new,

//	.imem = nv50_instmem_new,

	.imem = nv50_instmem_new,

//	.ltc = gf100_ltc_new,

//	.mc = gf100_mc_new,

//	.mmu = gf100_mmu_new,
@@ -1334,7 +1334,7 @@ nvc1_chipset = { 
	.gpio = g94_gpio_new,

	.i2c = g94_i2c_new,

	.ibus = gf100_ibus_new,

//	.imem = nv50_instmem_new,

	.imem = nv50_instmem_new,

//	.ltc = gf100_ltc_new,

//	.mc = gf106_mc_new,

//	.mmu = gf100_mmu_new,
@@ -1368,7 +1368,7 @@ nvc3_chipset = { 
	.gpio = g94_gpio_new,

	.i2c = g94_i2c_new,

	.ibus = gf100_ibus_new,

//	.imem = nv50_instmem_new,

	.imem = nv50_instmem_new,

//	.ltc = gf100_ltc_new,

//	.mc = gf106_mc_new,

//	.mmu = gf100_mmu_new,
@@ -1402,7 +1402,7 @@ nvc4_chipset = { 
	.gpio = g94_gpio_new,

	.i2c = g94_i2c_new,

	.ibus = gf100_ibus_new,

//	.imem = nv50_instmem_new,

	.imem = nv50_instmem_new,

//	.ltc = gf100_ltc_new,

//	.mc = gf100_mc_new,

//	.mmu = gf100_mmu_new,
@@ -1437,7 +1437,7 @@ nvc8_chipset = { 
	.gpio = g94_gpio_new,

	.i2c = g94_i2c_new,

	.ibus = gf100_ibus_new,

//	.imem = nv50_instmem_new,

	.imem = nv50_instmem_new,

//	.ltc = gf100_ltc_new,

//	.mc = gf100_mc_new,

//	.mmu = gf100_mmu_new,
@@ -1472,7 +1472,7 @@ nvce_chipset = { 
	.gpio = g94_gpio_new,

	.i2c = g94_i2c_new,

	.ibus = gf100_ibus_new,

//	.imem = nv50_instmem_new,

	.imem = nv50_instmem_new,

//	.ltc = gf100_ltc_new,

//	.mc = gf100_mc_new,

//	.mmu = gf100_mmu_new,
@@ -1507,7 +1507,7 @@ nvcf_chipset = { 
	.gpio = g94_gpio_new,

	.i2c = g94_i2c_new,

	.ibus = gf100_ibus_new,

//	.imem = nv50_instmem_new,

	.imem = nv50_instmem_new,

//	.ltc = gf100_ltc_new,

//	.mc = gf106_mc_new,

//	.mmu = gf100_mmu_new,
@@ -1541,7 +1541,7 @@ nvd7_chipset = { 
	.gpio = gf119_gpio_new,

	.i2c = gf117_i2c_new,

	.ibus = gf100_ibus_new,

//	.imem = nv50_instmem_new,

	.imem = nv50_instmem_new,

//	.ltc = gf100_ltc_new,

//	.mc = gf106_mc_new,

//	.mmu = gf100_mmu_new,
@@ -1573,7 +1573,7 @@ nvd9_chipset = { 
	.gpio = gf119_gpio_new,

	.i2c = gf119_i2c_new,

	.ibus = gf100_ibus_new,

//	.imem = nv50_instmem_new,

	.imem = nv50_instmem_new,

//	.ltc = gf100_ltc_new,

//	.mc = gf106_mc_new,

//	.mmu = gf100_mmu_new,
@@ -1607,7 +1607,7 @@ nve4_chipset = { 
	.gpio = gk104_gpio_new,

	.i2c = gk104_i2c_new,

	.ibus = gk104_ibus_new,

//	.imem = nv50_instmem_new,

	.imem = nv50_instmem_new,

//	.ltc = gk104_ltc_new,

//	.mc = gf106_mc_new,

//	.mmu = gf100_mmu_new,
@@ -1643,7 +1643,7 @@ nve6_chipset = { 
	.gpio = gk104_gpio_new,

	.i2c = gk104_i2c_new,

	.ibus = gk104_ibus_new,

//	.imem = nv50_instmem_new,

	.imem = nv50_instmem_new,

//	.ltc = gk104_ltc_new,

//	.mc = gf106_mc_new,

//	.mmu = gf100_mmu_new,
@@ -1679,7 +1679,7 @@ nve7_chipset = { 
	.gpio = gk104_gpio_new,

	.i2c = gk104_i2c_new,

	.ibus = gk104_ibus_new,

//	.imem = nv50_instmem_new,

	.imem = nv50_instmem_new,

//	.ltc = gk104_ltc_new,

//	.mc = gf106_mc_new,

//	.mmu = gf100_mmu_new,
@@ -1711,7 +1711,7 @@ nvea_chipset = { 
	.fb = gk20a_fb_new,

	.fuse = gf100_fuse_new,

	.ibus = gk20a_ibus_new,

//	.imem = gk20a_instmem_new,

	.imem = gk20a_instmem_new,

//	.ltc = gk104_ltc_new,

//	.mc = gk20a_mc_new,

//	.mmu = gf100_mmu_new,
@@ -1739,7 +1739,7 @@ nvf0_chipset = { 
	.gpio = gk104_gpio_new,

	.i2c = gk104_i2c_new,

	.ibus = gk104_ibus_new,

//	.imem = nv50_instmem_new,

	.imem = nv50_instmem_new,

//	.ltc = gk104_ltc_new,

//	.mc = gf106_mc_new,

//	.mmu = gf100_mmu_new,
@@ -1775,7 +1775,7 @@ nvf1_chipset = { 
	.gpio = gk104_gpio_new,

	.i2c = gf119_i2c_new,

	.ibus = gk104_ibus_new,

//	.imem = nv50_instmem_new,

	.imem = nv50_instmem_new,

//	.ltc = gk104_ltc_new,

//	.mc = gf106_mc_new,

//	.mmu = gf100_mmu_new,
@@ -1811,7 +1811,7 @@ nv106_chipset = { 
	.gpio = gk104_gpio_new,

	.i2c = gk104_i2c_new,

	.ibus = gk104_ibus_new,

//	.imem = nv50_instmem_new,

	.imem = nv50_instmem_new,

//	.ltc = gk104_ltc_new,

//	.mc = gk20a_mc_new,

//	.mmu = gf100_mmu_new,
@@ -1846,7 +1846,7 @@ nv108_chipset = { 
	.gpio = gk104_gpio_new,

	.i2c = gk104_i2c_new,

	.ibus = gk104_ibus_new,

//	.imem = nv50_instmem_new,

	.imem = nv50_instmem_new,

//	.ltc = gk104_ltc_new,

//	.mc = gk20a_mc_new,

//	.mmu = gf100_mmu_new,
@@ -1881,7 +1881,7 @@ nv117_chipset = { 
	.gpio = gk104_gpio_new,

	.i2c = gf119_i2c_new,

	.ibus = gk104_ibus_new,

//	.imem = nv50_instmem_new,

	.imem = nv50_instmem_new,

//	.ltc = gm107_ltc_new,

//	.mc = gk20a_mc_new,

//	.mmu = gf100_mmu_new,
@@ -1910,7 +1910,7 @@ nv124_chipset = { 
	.gpio = gk104_gpio_new,

	.i2c = gm204_i2c_new,

	.ibus = gk104_ibus_new,

//	.imem = nv50_instmem_new,

	.imem = nv50_instmem_new,

//	.ltc = gm107_ltc_new,

//	.mc = gk20a_mc_new,

//	.mmu = gf100_mmu_new,
@@ -1939,7 +1939,7 @@ nv126_chipset = { 
	.gpio = gk104_gpio_new,

	.i2c = gm204_i2c_new,

	.ibus = gk104_ibus_new,

//	.imem = nv50_instmem_new,

	.imem = nv50_instmem_new,

//	.ltc = gm107_ltc_new,

//	.mc = gk20a_mc_new,

//	.mmu = gf100_mmu_new,
@@ -1964,7 +1964,7 @@ nv12b_chipset = { 
	.fb = gk20a_fb_new,

	.fuse = gm107_fuse_new,

	.ibus = gk20a_ibus_new,

//	.imem = gk20a_instmem_new,

	.imem = gk20a_instmem_new,

//	.ltc = gm107_ltc_new,

//	.mc = gk20a_mc_new,

//	.mmu = gf100_mmu_new,

drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c

+0 −9
Original line number Diff line number Diff line
@@ -33,7 +33,6 @@ gf100_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_SUBDEV_MC     ] =  gf100_mc_oclass;

		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;

		device->oclass[NVDEV_SUBDEV_LTC    ] =  gf100_ltc_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_MMU    ] = &gf100_mmu_oclass;

		device->oclass[NVDEV_SUBDEV_PMU    ] =  gf100_pmu_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
@@ -55,7 +54,6 @@ gf100_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_SUBDEV_MC     ] =  gf100_mc_oclass;

		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;

		device->oclass[NVDEV_SUBDEV_LTC    ] =  gf100_ltc_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_MMU    ] = &gf100_mmu_oclass;

		device->oclass[NVDEV_SUBDEV_PMU    ] =  gf100_pmu_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
@@ -77,7 +75,6 @@ gf100_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_SUBDEV_MC     ] =  gf106_mc_oclass;

		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;

		device->oclass[NVDEV_SUBDEV_LTC    ] =  gf100_ltc_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_MMU    ] = &gf100_mmu_oclass;

		device->oclass[NVDEV_SUBDEV_PMU    ] =  gf100_pmu_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
@@ -98,7 +95,6 @@ gf100_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_SUBDEV_MC     ] =  gf100_mc_oclass;

		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;

		device->oclass[NVDEV_SUBDEV_LTC    ] =  gf100_ltc_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_MMU    ] = &gf100_mmu_oclass;

		device->oclass[NVDEV_SUBDEV_PMU    ] =  gf100_pmu_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
@@ -120,7 +116,6 @@ gf100_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_SUBDEV_MC     ] =  gf106_mc_oclass;

		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;

		device->oclass[NVDEV_SUBDEV_LTC    ] =  gf100_ltc_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_MMU    ] = &gf100_mmu_oclass;

		device->oclass[NVDEV_SUBDEV_PMU    ] =  gf100_pmu_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
@@ -141,7 +136,6 @@ gf100_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_SUBDEV_MC     ] =  gf106_mc_oclass;

		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;

		device->oclass[NVDEV_SUBDEV_LTC    ] =  gf100_ltc_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_MMU    ] = &gf100_mmu_oclass;

		device->oclass[NVDEV_SUBDEV_PMU    ] =  gf100_pmu_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
@@ -162,7 +156,6 @@ gf100_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_SUBDEV_MC     ] =  gf100_mc_oclass;

		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;

		device->oclass[NVDEV_SUBDEV_LTC    ] =  gf100_ltc_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_MMU    ] = &gf100_mmu_oclass;

		device->oclass[NVDEV_SUBDEV_PMU    ] =  gf100_pmu_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
@@ -184,7 +177,6 @@ gf100_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_SUBDEV_MC     ] =  gf106_mc_oclass;

		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;

		device->oclass[NVDEV_SUBDEV_LTC    ] =  gf100_ltc_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_MMU    ] = &gf100_mmu_oclass;

		device->oclass[NVDEV_SUBDEV_PMU    ] =  gf110_pmu_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
@@ -205,7 +197,6 @@ gf100_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_SUBDEV_MC     ] =  gf106_mc_oclass;

		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;

		device->oclass[NVDEV_SUBDEV_LTC    ] =  gf100_ltc_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_MMU    ] = &gf100_mmu_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;

drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c

+0 −8
Original line number Diff line number Diff line
@@ -33,7 +33,6 @@ gk104_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_SUBDEV_MC     ] =  gf106_mc_oclass;

		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;

		device->oclass[NVDEV_SUBDEV_LTC    ] =  gk104_ltc_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_MMU    ] = &gf100_mmu_oclass;

		device->oclass[NVDEV_SUBDEV_PMU    ] =  gk104_pmu_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
@@ -56,7 +55,6 @@ gk104_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_SUBDEV_MC     ] =  gf106_mc_oclass;

		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;

		device->oclass[NVDEV_SUBDEV_LTC    ] =  gk104_ltc_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_MMU    ] = &gf100_mmu_oclass;

		device->oclass[NVDEV_SUBDEV_PMU    ] =  gf110_pmu_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
@@ -79,7 +77,6 @@ gk104_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_SUBDEV_MC     ] =  gf106_mc_oclass;

		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;

		device->oclass[NVDEV_SUBDEV_LTC    ] =  gk104_ltc_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_MMU    ] = &gf100_mmu_oclass;

		device->oclass[NVDEV_SUBDEV_PMU    ] =  gk104_pmu_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
@@ -100,7 +97,6 @@ gk104_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_SUBDEV_MC     ] =  gk20a_mc_oclass;

		device->oclass[NVDEV_SUBDEV_TIMER  ] = &gk20a_timer_oclass;

		device->oclass[NVDEV_SUBDEV_LTC    ] =  gk104_ltc_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] = gk20a_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_MMU    ] = &gf100_mmu_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gk20a_fifo_oclass;
@@ -117,7 +113,6 @@ gk104_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_SUBDEV_MC     ] =  gf106_mc_oclass;

		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;

		device->oclass[NVDEV_SUBDEV_LTC    ] =  gk104_ltc_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_MMU    ] = &gf100_mmu_oclass;

		device->oclass[NVDEV_SUBDEV_PMU    ] =  gk110_pmu_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
@@ -140,7 +135,6 @@ gk104_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_SUBDEV_MC     ] =  gf106_mc_oclass;

		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;

		device->oclass[NVDEV_SUBDEV_LTC    ] =  gk104_ltc_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_MMU    ] = &gf100_mmu_oclass;

		device->oclass[NVDEV_SUBDEV_PMU    ] =  gk110_pmu_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
@@ -163,7 +157,6 @@ gk104_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_SUBDEV_MC     ] =  gk20a_mc_oclass;

		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;

		device->oclass[NVDEV_SUBDEV_LTC    ] =  gk104_ltc_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_MMU    ] = &gf100_mmu_oclass;

		device->oclass[NVDEV_SUBDEV_PMU    ] =  gk208_pmu_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
@@ -185,7 +178,6 @@ gk104_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_SUBDEV_MC     ] =  gk20a_mc_oclass;

		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;

		device->oclass[NVDEV_SUBDEV_LTC    ] =  gk104_ltc_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_MMU    ] = &gf100_mmu_oclass;

		device->oclass[NVDEV_SUBDEV_PMU    ] =  gk208_pmu_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

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