Commit b77d643c authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/upstream-linus 

* 'upstream' of git://git.linux-mips.org/pub/scm/upstream-linus: (46 commits)
  ftrace/MIPS: Enable C Version of recordmcount
  ftrace/MIPS: Add module support for C version of recordmcount
  ftrace/MIPS: Add MIPS64 support for C version of recordmcount
  MIPS: Make TASK_SIZE reflect proper size for both 32 and 64 bit processes.
  MIPS: Allow UserLocal on MIPS_R1 processors
  MIPS: Honor L2 bypass bit
  MIPS: Add BMIPS CP0 register definitions
  MIPS: Add BMIPS processor types to Kconfig
  MIPS: Decouple BMIPS CPU support from bcm47xx/bcm63xx SoC code
  MIPS: Add support for hardware performance events (mipsxx)
  MIPS: Perf-events: Add callchain support
  MIPS: add support for hardware performance events (skeleton)
  MIPS: add support for software performance events
  MIPS: define local_xchg from xchg_local to atomic_long_xchg
  MIPS: AR7: Add support for Titan (TNETV10xx) SoC variant
  MIPS: AR7: Initialize GPIO earlier
  MIPS: Add platform device and Kconfig for Octeon USB EHCI / OHCI
  USB: Add EHCI and OHCH glue for OCTEON II SOCs.
  MIPS: Octeon: Add register definitions for EHCI / OHCI USB glue logic.
  MIPS: Octeon: Apply CN63XXP1 errata workarounds.
  ...
parents b4020c1b 64575f91

arch/mips/Kconfig

+79 −0
Original line number Diff line number Diff line
@@ -4,16 +4,21 @@ config MIPS 
	select HAVE_GENERIC_DMA_COHERENT

	select HAVE_IDE

	select HAVE_OPROFILE

	select HAVE_PERF_EVENTS

	select PERF_USE_VMALLOC

	select HAVE_ARCH_KGDB

	select HAVE_FUNCTION_TRACER

	select HAVE_FUNCTION_TRACE_MCOUNT_TEST

	select HAVE_DYNAMIC_FTRACE

	select HAVE_FTRACE_MCOUNT_RECORD

	select HAVE_C_RECORDMCOUNT

	select HAVE_FUNCTION_GRAPH_TRACER

	select HAVE_KPROBES

	select HAVE_KRETPROBES

	select RTC_LIB if !MACH_LOONGSON

	select GENERIC_ATOMIC64 if !64BIT

	select HAVE_DMA_ATTRS

	select HAVE_DMA_API_DEBUG



menu "Machine selection"
@@ -691,6 +696,9 @@ config CAVIUM_OCTEON_REFERENCE_BOARD 
	select SWAP_IO_SPACE

	select HW_HAS_PCI

	select ARCH_SUPPORTS_MSI

	select ZONE_DMA32

	select USB_ARCH_HAS_OHCI

	select USB_ARCH_HAS_EHCI

	help

	  This option supports all of the Octeon reference boards from Cavium

	  Networks. It builds a kernel that dynamically determines the Octeon
@@ -1334,6 +1342,57 @@ config CPU_CAVIUM_OCTEON 
	  can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.

	  Full details can be found at http://www.caviumnetworks.com.



config CPU_BMIPS3300

	bool "BMIPS3300"

	depends on SYS_HAS_CPU_BMIPS3300

	select DMA_NONCOHERENT

	select IRQ_CPU

	select SWAP_IO_SPACE

	select SYS_SUPPORTS_32BIT_KERNEL

	select WEAK_ORDERING

	help

	  Broadcom BMIPS3300 processors.



config CPU_BMIPS4350

	bool "BMIPS4350"

	depends on SYS_HAS_CPU_BMIPS4350

	select CPU_SUPPORTS_32BIT_KERNEL

	select DMA_NONCOHERENT

	select IRQ_CPU

	select SWAP_IO_SPACE

	select SYS_SUPPORTS_SMP

	select SYS_SUPPORTS_HOTPLUG_CPU

	select WEAK_ORDERING

	help

	  Broadcom BMIPS4350 ("VIPER") processors.



config CPU_BMIPS4380

	bool "BMIPS4380"

	depends on SYS_HAS_CPU_BMIPS4380

	select CPU_SUPPORTS_32BIT_KERNEL

	select DMA_NONCOHERENT

	select IRQ_CPU

	select SWAP_IO_SPACE

	select SYS_SUPPORTS_SMP

	select SYS_SUPPORTS_HOTPLUG_CPU

	select WEAK_ORDERING

	help

	  Broadcom BMIPS4380 processors.



config CPU_BMIPS5000

	bool "BMIPS5000"

	depends on SYS_HAS_CPU_BMIPS5000

	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_HIGHMEM

	select DMA_NONCOHERENT

	select IRQ_CPU

	select SWAP_IO_SPACE

	select SYS_SUPPORTS_SMP

	select SYS_SUPPORTS_HOTPLUG_CPU

	select WEAK_ORDERING

	help

	  Broadcom BMIPS5000 processors.



endchoice



if CPU_LOONGSON2F
@@ -1452,6 +1511,18 @@ config SYS_HAS_CPU_SB1 
config SYS_HAS_CPU_CAVIUM_OCTEON

	bool



config SYS_HAS_CPU_BMIPS3300

	bool



config SYS_HAS_CPU_BMIPS4350

	bool



config SYS_HAS_CPU_BMIPS4380

	bool



config SYS_HAS_CPU_BMIPS5000

	bool



#

# CPU may reorder R->R, R->W, W->R, W->W

# Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
@@ -1928,6 +1999,14 @@ config NODES_SHIFT 
	default "6"

	depends on NEED_MULTIPLE_NODES



config HW_PERF_EVENTS

	bool "Enable hardware performance counter support for perf events"

	depends on PERF_EVENTS && !MIPS_MT_SMTC && OPROFILE=n && CPU_MIPS32

	default y

	help

	  Enable hardware performance counter support for perf events. If

	  disabled, perf events will use software events only.



source "mm/Kconfig"



config SMP

arch/mips/Kconfig.debug

+9 −0
Original line number Diff line number Diff line
@@ -67,6 +67,15 @@ config CMDLINE_OVERRIDE 


	  Normally, you will choose 'N' here.



config DEBUG_STACKOVERFLOW

	bool "Check for stack overflows"

	depends on DEBUG_KERNEL

	help

	  This option will cause messages to be printed if free stack space

	  drops below a certain limit(2GB on MIPS). The debugging option

	  provides another way to check stack overflow happened on kernel mode

	  stack usually caused by nested interruption.



config DEBUG_STACK_USAGE

	bool "Enable stack utilization instrumentation"

	depends on DEBUG_KERNEL

arch/mips/Makefile

+1 −3
Original line number Diff line number Diff line
@@ -48,9 +48,6 @@ ifneq ($(SUBARCH),$(ARCH)) 
  endif

endif



ifndef CONFIG_FUNCTION_TRACER

cflags-y := -ffunction-sections

endif

ifdef CONFIG_FUNCTION_GRAPH_TRACER

  ifndef KBUILD_MCOUNT_RA_ADDRESS

    ifeq ($(call cc-option-yn,-mmcount-ra-address), y)
@@ -159,6 +156,7 @@ cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += $(call cc-option,-march=octeon) -Wa,--trap 
ifeq (,$(findstring march=octeon, $(cflags-$(CONFIG_CPU_CAVIUM_OCTEON))))

cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -Wa,-march=octeon

endif

cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1



cflags-$(CONFIG_CPU_R4000_WORKAROUNDS)	+= $(call cc-option,-mfix-r4000,)

cflags-$(CONFIG_CPU_R4400_WORKAROUNDS)	+= $(call cc-option,-mfix-r4400,)

arch/mips/ar7/gpio.c

+231 −12
Original line number Diff line number Diff line 
/*

 * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>

 * Copyright (C) 2007 Eugene Konev <ejka@openwrt.org>

 * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>

 * Copyright (C) 2009-2010 Florian Fainelli <florian@openwrt.org>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by
@@ -37,6 +37,16 @@ static int ar7_gpio_get_value(struct gpio_chip *chip, unsigned gpio) 
	return readl(gpio_in) & (1 << gpio);

}



static int titan_gpio_get_value(struct gpio_chip *chip, unsigned gpio)

{

	struct ar7_gpio_chip *gpch =

				container_of(chip, struct ar7_gpio_chip, chip);

	void __iomem *gpio_in0 = gpch->regs + TITAN_GPIO_INPUT_0;

	void __iomem *gpio_in1 = gpch->regs + TITAN_GPIO_INPUT_1;



	return readl(gpio >> 5 ? gpio_in1 : gpio_in0) & (1 << (gpio & 0x1f));

}



static void ar7_gpio_set_value(struct gpio_chip *chip,

				unsigned gpio, int value)

{
@@ -51,6 +61,21 @@ static void ar7_gpio_set_value(struct gpio_chip *chip, 
	writel(tmp, gpio_out);

}



static void titan_gpio_set_value(struct gpio_chip *chip,

				unsigned gpio, int value)

{

	struct ar7_gpio_chip *gpch =

				container_of(chip, struct ar7_gpio_chip, chip);

	void __iomem *gpio_out0 = gpch->regs + TITAN_GPIO_OUTPUT_0;

	void __iomem *gpio_out1 = gpch->regs + TITAN_GPIO_OUTPUT_1;

	unsigned tmp;



	tmp = readl(gpio >> 5 ? gpio_out1 : gpio_out0) & ~(1 << (gpio & 0x1f));

	if (value)

		tmp |= 1 << (gpio & 0x1f);

	writel(tmp, gpio >> 5 ? gpio_out1 : gpio_out0);

}



static int ar7_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)

{

	struct ar7_gpio_chip *gpch =
@@ -62,6 +87,21 @@ static int ar7_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) 
	return 0;

}



static int titan_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)

{

	struct ar7_gpio_chip *gpch =

				container_of(chip, struct ar7_gpio_chip, chip);

	void __iomem *gpio_dir0 = gpch->regs + TITAN_GPIO_DIR_0;

	void __iomem *gpio_dir1 = gpch->regs + TITAN_GPIO_DIR_1;



	if (gpio >= TITAN_GPIO_MAX)

		return -EINVAL;



	writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) | (1 << (gpio & 0x1f)),

			gpio >> 5 ? gpio_dir1 : gpio_dir0);

	return 0;

}



static int ar7_gpio_direction_output(struct gpio_chip *chip,

					unsigned gpio, int value)

{
@@ -75,6 +115,24 @@ static int ar7_gpio_direction_output(struct gpio_chip *chip, 
	return 0;

}



static int titan_gpio_direction_output(struct gpio_chip *chip,

					unsigned gpio, int value)

{

	struct ar7_gpio_chip *gpch =

				container_of(chip, struct ar7_gpio_chip, chip);

	void __iomem *gpio_dir0 = gpch->regs + TITAN_GPIO_DIR_0;

	void __iomem *gpio_dir1 = gpch->regs + TITAN_GPIO_DIR_1;



	if (gpio >= TITAN_GPIO_MAX)

		return -EINVAL;



	titan_gpio_set_value(chip, gpio, value);

	writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) & ~(1 <<

		(gpio & 0x1f)), gpio >> 5 ? gpio_dir1 : gpio_dir0);



	return 0;

}



static struct ar7_gpio_chip ar7_gpio_chip = {

	.chip = {

		.label			= "ar7-gpio",
@@ -87,7 +145,19 @@ static struct ar7_gpio_chip ar7_gpio_chip = { 
	}

};



int ar7_gpio_enable(unsigned gpio)

static struct ar7_gpio_chip titan_gpio_chip = {

	.chip = {

		.label			= "titan-gpio",

		.direction_input	= titan_gpio_direction_input,

		.direction_output	= titan_gpio_direction_output,

		.set			= titan_gpio_set_value,

		.get			= titan_gpio_get_value,

		.base			= 0,

		.ngpio			= TITAN_GPIO_MAX,

	}

};



static inline int ar7_gpio_enable_ar7(unsigned gpio)

{

	void __iomem *gpio_en = ar7_gpio_chip.regs + AR7_GPIO_ENABLE;
@@ -95,9 +165,26 @@ int ar7_gpio_enable(unsigned gpio) 


	return 0;

}



static inline int ar7_gpio_enable_titan(unsigned gpio)

{

	void __iomem *gpio_en0 = titan_gpio_chip.regs  + TITAN_GPIO_ENBL_0;

	void __iomem *gpio_en1 = titan_gpio_chip.regs  + TITAN_GPIO_ENBL_1;



	writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) | (1 << (gpio & 0x1f)),

		gpio >> 5 ? gpio_en1 : gpio_en0);



	return 0;

}



int ar7_gpio_enable(unsigned gpio)

{

	return ar7_is_titan() ? ar7_gpio_enable_titan(gpio) :

				ar7_gpio_enable_ar7(gpio);

}

EXPORT_SYMBOL(ar7_gpio_enable);



int ar7_gpio_disable(unsigned gpio)

static inline int ar7_gpio_disable_ar7(unsigned gpio)

{

	void __iomem *gpio_en = ar7_gpio_chip.regs + AR7_GPIO_ENABLE;
@@ -105,27 +192,159 @@ int ar7_gpio_disable(unsigned gpio) 


	return 0;

}



static inline int ar7_gpio_disable_titan(unsigned gpio)

{

	void __iomem *gpio_en0 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_0;

	void __iomem *gpio_en1 = titan_gpio_chip.regs + TITAN_GPIO_ENBL_1;



	writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) & ~(1 << (gpio & 0x1f)),

			gpio >> 5 ? gpio_en1 : gpio_en0);



	return 0;

}



int ar7_gpio_disable(unsigned gpio)

{

	return ar7_is_titan() ? ar7_gpio_disable_titan(gpio) :

				ar7_gpio_disable_ar7(gpio);

}

EXPORT_SYMBOL(ar7_gpio_disable);



static int __init ar7_gpio_init(void)

struct titan_gpio_cfg {

	u32 reg;

	u32 shift;

	u32 func;

};



static struct titan_gpio_cfg titan_gpio_table[] = {

	/* reg, start bit, mux value */

	{4, 24, 1},

	{4, 26, 1},

	{4, 28, 1},

	{4, 30, 1},

	{5, 6, 1},

	{5, 8, 1},

	{5, 10, 1},

	{5, 12, 1},

	{7, 14, 3},

	{7, 16, 3},

	{7, 18, 3},

	{7, 20, 3},

	{7, 22, 3},

	{7, 26, 3},

	{7, 28, 3},

	{7, 30, 3},

	{8, 0, 3},

	{8, 2, 3},

	{8, 4, 3},

	{8, 10, 3},

	{8, 14, 3},

	{8, 16, 3},

	{8, 18, 3},

	{8, 20, 3},

	{9, 8, 3},

	{9, 10, 3},

	{9, 12, 3},

	{9, 14, 3},

	{9, 18, 3},

	{9, 20, 3},

	{9, 24, 3},

	{9, 26, 3},

	{9, 28, 3},

	{9, 30, 3},

	{10, 0, 3},

	{10, 2, 3},

	{10, 8, 3},

	{10, 10, 3},

	{10, 12, 3},

	{10, 14, 3},

	{13, 12, 3},

	{13, 14, 3},

	{13, 16, 3},

	{13, 18, 3},

	{13, 24, 3},

	{13, 26, 3},

	{13, 28, 3},

	{13, 30, 3},

	{14, 2, 3},

	{14, 6, 3},

	{14, 8, 3},

	{14, 12, 3}

};



static int titan_gpio_pinsel(unsigned gpio)

{

	struct titan_gpio_cfg gpio_cfg;

	u32 mux_status, pin_sel_reg, tmp;

	void __iomem *pin_sel = (void __iomem *)KSEG1ADDR(AR7_REGS_PINSEL);



	if (gpio >= ARRAY_SIZE(titan_gpio_table))

		return -EINVAL;



	gpio_cfg = titan_gpio_table[gpio];

	pin_sel_reg = gpio_cfg.reg - 1;



	mux_status = (readl(pin_sel + pin_sel_reg) >> gpio_cfg.shift) & 0x3;



	/* Check the mux status */

	if (!((mux_status == 0) || (mux_status == gpio_cfg.func)))

		return 0;



	/* Set the pin sel value */

	tmp = readl(pin_sel + pin_sel_reg);

	tmp |= ((gpio_cfg.func & 0x3) << gpio_cfg.shift);

	writel(tmp, pin_sel + pin_sel_reg);



	return 0;

}



/* Perform minimal Titan GPIO configuration */

static void titan_gpio_init(void)

{

	unsigned i;



	for (i = 44; i < 48; i++) {

		titan_gpio_pinsel(i);

		ar7_gpio_enable_titan(i);

		titan_gpio_direction_input(&titan_gpio_chip.chip, i);

	}

}



int __init ar7_gpio_init(void)

{

	int ret;

	struct ar7_gpio_chip *gpch;

	unsigned size;



	if (!ar7_is_titan()) {

		gpch = &ar7_gpio_chip;

		size = 0x10;

	} else {

		gpch = &titan_gpio_chip;

		size = 0x1f;

	}



	ar7_gpio_chip.regs = ioremap_nocache(AR7_REGS_GPIO,

	gpch->regs = ioremap_nocache(AR7_REGS_GPIO,

					AR7_REGS_GPIO + 0x10);



	if (!ar7_gpio_chip.regs) {

		printk(KERN_ERR "ar7-gpio: failed to ioremap regs\n");

	if (!gpch->regs) {

		printk(KERN_ERR "%s: failed to ioremap regs\n",

					gpch->chip.label);

		return -ENOMEM;

	}



	ret = gpiochip_add(&ar7_gpio_chip.chip);

	ret = gpiochip_add(&gpch->chip);

	if (ret) {

		printk(KERN_ERR "ar7-gpio: failed to add gpiochip\n");

		printk(KERN_ERR "%s: failed to add gpiochip\n",

					gpch->chip.label);

		return ret;

	}

	printk(KERN_INFO "ar7-gpio: registered %d GPIOs\n",

				ar7_gpio_chip.chip.ngpio);

	printk(KERN_INFO "%s: registered %d GPIOs\n",

				gpch->chip.label, gpch->chip.ngpio);



	if (ar7_is_titan())

		titan_gpio_init();



	return ret;

}
 
arch_initcall(ar7_gpio_init);

arch/mips/ar7/platform.c

+56 −0
Original line number Diff line number Diff line
@@ -357,6 +357,11 @@ static struct gpio_led default_leds[] = { 
	},

};



static struct gpio_led titan_leds[] = {

	{ .name = "status", .gpio = 8, .active_low = 1, },

	{ .name = "wifi", .gpio = 13, .active_low = 1, },

};



static struct gpio_led dsl502t_leds[] = {

	{

		.name			= "status",
@@ -495,6 +500,9 @@ static void __init detect_leds(void) 
	} else if (strstr(prid, "DG834")) {

		ar7_led_data.num_leds = ARRAY_SIZE(dg834g_leds);

		ar7_led_data.leds = dg834g_leds;

	} else if (strstr(prid, "CYWM") || strstr(prid, "CYWL")) {

		ar7_led_data.num_leds = ARRAY_SIZE(titan_leds);

		ar7_led_data.leds = titan_leds;

	}

}
@@ -560,6 +568,51 @@ static int __init ar7_register_uarts(void) 
	return 0;

}



static void __init titan_fixup_devices(void)

{

	/* Set vlynq0 data */

	vlynq_low_data.reset_bit = 15;

	vlynq_low_data.gpio_bit = 14;



	/* Set vlynq1 data */

	vlynq_high_data.reset_bit = 16;

	vlynq_high_data.gpio_bit = 7;



	/* Set vlynq0 resources */

	vlynq_low_res[0].start = TITAN_REGS_VLYNQ0;

	vlynq_low_res[0].end = TITAN_REGS_VLYNQ0 + 0xff;

	vlynq_low_res[1].start = 33;

	vlynq_low_res[1].end = 33;

	vlynq_low_res[2].start = 0x0c000000;

	vlynq_low_res[2].end = 0x0fffffff;

	vlynq_low_res[3].start = 80;

	vlynq_low_res[3].end = 111;



	/* Set vlynq1 resources */

	vlynq_high_res[0].start = TITAN_REGS_VLYNQ1;

	vlynq_high_res[0].end = TITAN_REGS_VLYNQ1 + 0xff;

	vlynq_high_res[1].start = 34;

	vlynq_high_res[1].end = 34;

	vlynq_high_res[2].start = 0x40000000;

	vlynq_high_res[2].end = 0x43ffffff;

	vlynq_high_res[3].start = 112;

	vlynq_high_res[3].end = 143;



	/* Set cpmac0 data */

	cpmac_low_data.phy_mask = 0x40000000;



	/* Set cpmac1 data */

	cpmac_high_data.phy_mask = 0x80000000;



	/* Set cpmac0 resources */

	cpmac_low_res[0].start = TITAN_REGS_MAC0;

	cpmac_low_res[0].end = TITAN_REGS_MAC0 + 0x7ff;



	/* Set cpmac1 resources */

	cpmac_high_res[0].start = TITAN_REGS_MAC1;

	cpmac_high_res[0].end = TITAN_REGS_MAC1 + 0x7ff;

}



static int __init ar7_register_devices(void)

{

	void __iomem *bootcr;
@@ -574,6 +627,9 @@ static int __init ar7_register_devices(void) 
	if (res)

		pr_warning("unable to register physmap-flash: %d\n", res);



	if (ar7_is_titan())

		titan_fixup_devices();



	ar7_device_disable(vlynq_low_data.reset_bit);

	res = platform_device_register(&vlynq_low);

	if (res)

CRA Git | Maintained and supported by SUSTech CRA and CCSE