bnx2x: Split PHY functions (b7737c9b) · Commits · 戴 / test

drivers/net/bnx2x/bnx2x_ethtool.c

+5 −30

Original line number	Diff line number	Diff line
		@@ -52,39 +52,14 @@ static int bnx2x_get_settings(struct net_device dev, struct ethtool_cmd cmd)
		cmd->duplex = -1;
		}

		if (bp->link_params.switch_cfg == SWITCH_CFG_10G) {
		u32 ext_phy_type =
		XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);

		switch (ext_phy_type) {
		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
		if (bp->link_params.num_phys > 0) {
		if (bp->link_params.phy[bp->link_params.num_phys - 1].
		supported & SUPPORTED_FIBRE)
		cmd->port = PORT_FIBRE;
		break;

		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
		else
		cmd->port = PORT_TP;
		break;

		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
		BNX2X_ERR("XGXS PHY Failure detected 0x%x\n",
		bp->link_params.ext_phy_config);
		break;

		default:
		DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
		bp->link_params.ext_phy_config);
		break;
		}
		} else
		cmd->port = PORT_TP;

		DP(NETIF_MSG_LINK, "No media found\n");
		cmd->phy_address = bp->mdio.prtad;
		cmd->transceiver = XCVR_INTERNAL;

drivers/net/bnx2x/bnx2x_link.c

+1293 −571

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/bnx2x/bnx2x_link.h

+91 −18

Original line number	Diff line number	Diff line
		@@ -46,6 +46,15 @@
		#define SFP_EEPROM_PART_NO_ADDR 0x28
		#define SFP_EEPROM_PART_NO_SIZE 16
		#define PWR_FLT_ERR_MSG_LEN 250

		#define XGXS_EXT_PHY_TYPE(ext_phy_config) \
		((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
		#define XGXS_EXT_PHY_ADDR(ext_phy_config) \
		(((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \
		PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT)
		#define SERDES_EXT_PHY_TYPE(ext_phy_config) \
		((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)

		/* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */
		#define SINGLE_MEDIA_DIRECT(params) (params->num_phys == 1)
		/* Single Media board contains single external phy */
		@@ -58,6 +67,10 @@

		#define MAX_PHYS 2

		/* Same configuration is shared between the XGXS and the first external phy */
		#define LINK_CONFIG_SIZE (MAX_PHYS - 1)
		#define LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == INT_PHY) ? \
		0 : (_phy_idx - 1))
		/***********************************************************/
		/* bnx2x_phy struct */
		/* Defines the required arguments and function per phy */
		@@ -66,13 +79,88 @@ struct link_vars;
		struct link_params;
		struct bnx2x_phy;

		typedef u8 (config_init_t)(struct bnx2x_phy phy, struct link_params *params,
		struct link_vars *vars);
		typedef u8 (read_status_t)(struct bnx2x_phy phy, struct link_params *params,
		struct link_vars *vars);
		typedef void (link_reset_t)(struct bnx2x_phy phy,
		struct link_params *params);
		typedef void (config_loopback_t)(struct bnx2x_phy phy,
		struct link_params *params);
		typedef u8 (format_fw_ver_t)(u32 raw, u8 str, u16 *len);
		typedef void (hw_reset_t)(struct bnx2x_phy phy, struct link_params *params);
		typedef void (set_link_led_t)(struct bnx2x_phy phy,
		struct link_params *params, u8 mode);

		struct bnx2x_phy {
		u32 type;

		/* Loaded during init */
		u8 addr;

		u8 flags;
		/* Require HW lock */
		#define FLAGS_HW_LOCK_REQUIRED (1<<0)
		/* No Over-Current detection */
		#define FLAGS_NOC (1<<1)
		/* Fan failure detection required */
		#define FLAGS_FAN_FAILURE_DET_REQ (1<<2)
		/* Initialize first the XGXS and only then the phy itself */
		#define FLAGS_INIT_XGXS_FIRST (1<<3)

		u8 def_md_devad;
		u8 reserved;
		/* preemphasis values for the rx side */
		u16 rx_preemphasis[4];

		/* preemphasis values for the tx side */
		u16 tx_preemphasis[4];

		/* EMAC address for access MDIO */
		u32 mdio_ctrl;

		u32 supported;

		u32 media_type;
		#define ETH_PHY_UNSPECIFIED 0x0
		#define ETH_PHY_SFP_FIBER 0x1
		#define ETH_PHY_XFP_FIBER 0x2
		#define ETH_PHY_DA_TWINAX 0x3
		#define ETH_PHY_BASE_T 0x4
		#define ETH_PHY_NOT_PRESENT 0xff

		/* The address in which version is located*/
		u32 ver_addr;

		u16 req_flow_ctrl;

		u16 req_line_speed;

		u32 speed_cap_mask;

		u16 req_duplex;
		u16 rsrv;
		/* Called per phy/port init, and it configures LASI, speed, autoneg,
		duplex, flow control negotiation, etc. */
		config_init_t config_init;

		/* Called due to interrupt. It determines the link, speed */
		read_status_t read_status;

		/* Called when driver is unloading. Should reset the phy */
		link_reset_t link_reset;

		/* Set the loopback configuration for the phy */
		config_loopback_t config_loopback;

		/* Format the given raw number into str up to len */
		format_fw_ver_t format_fw_ver;

		/* Reset the phy (both ports) */
		hw_reset_t hw_reset;

		/* Set link led mode (on/off/oper)*/
		set_link_led_t set_link_led;
		};

		/* Inputs parameters to the CLC */
		@@ -106,38 +194,23 @@ struct link_params {
		#define SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH
		#define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT

		u16 hw_led_mode; /* part of the hw_config read from the shmem */

		/* phy_addr populated by the phy_init function */
		u8 phy_addr;
		/u8 reserved1;/

		u32 lane_config;
		u32 ext_phy_config;
		#define XGXS_EXT_PHY_TYPE(ext_phy_config) \
		((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
		#define XGXS_EXT_PHY_ADDR(ext_phy_config) \
		(((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \
		PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT)
		#define SERDES_EXT_PHY_TYPE(ext_phy_config) \
		((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)

		/* Phy register parameter */
		u32 chip_id;

		u16 xgxs_config_rx[4]; /* preemphasis values for the rx side */
		u16 xgxs_config_tx[4]; /* preemphasis values for the tx side */

		u32 feature_config_flags;
		#define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)
		#define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2)
		#define FEATURE_CONFIG_BCM8727_NOC (1<<3)
		/* Will be populated during common init */
		struct bnx2x_phy phy[MAX_PHYS];

		/* Will be populated during common init */
		u8 num_phys;

		u8 rsrv;
		u16 hw_led_mode; /* part of the hw_config read from the shmem */

		/* Device pointer passed to all callback functions */
		struct bnx2x *bp;
		};

drivers/net/bnx2x/bnx2x_main.c

+36 −234

Original line number	Diff line number	Diff line
		@@ -1960,12 +1960,16 @@ static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
		static inline void bnx2x_fan_failure(struct bnx2x *bp)
		{
		int port = BP_PORT(bp);

		u32 ext_phy_config;
		/* mark the failure */
		bp->link_params.ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
		bp->link_params.ext_phy_config \|= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
		ext_phy_config =
		SHMEM_RD(bp,
		dev_info.port_hw_config[port].external_phy_config);

		ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
		ext_phy_config \|= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
		SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
		bp->link_params.ext_phy_config);
		ext_phy_config);

		/* log the failure */
		netdev_err(bp->dev, "Fan Failure on Network Controller has caused"
		@@ -1991,7 +1995,7 @@ static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
		BNX2X_ERR("SPIO5 hw attention\n");

		/* Fan failure attention */
		switch (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config)) {
		switch (bp->link_params.phy[EXT_PHY1].type) {
		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
		/* Low power mode is controlled by GPIO 2 */
		bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
		@@ -4140,7 +4144,7 @@ static int bnx2x_init_common(struct bnx2x *bp)
		return -EBUSY;
		}

		switch (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config)) {
		switch (bp->link_params.phy[EXT_PHY1].type) {
		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
		@@ -4299,7 +4303,7 @@ static int bnx2x_init_port(struct bnx2x *bp)
		bnx2x_init_block(bp, MCP_BLOCK, init_stage);
		bnx2x_init_block(bp, DMAE_BLOCK, init_stage);

		switch (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config)) {
		switch (bp->link_params.phy[EXT_PHY1].type) {
		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
		{
		u32 swap_val, swap_override, aeu_gpio_mask, offset;
		@@ -4480,7 +4484,7 @@ static int bnx2x_init_func(struct bnx2x *bp)
		/* Reset PCIE errors for debug */
		REG_WR(bp, 0x2114, 0xffffffff);
		REG_WR(bp, 0x2120, 0xffffffff);

		bnx2x_phy_probe(&bp->link_params);
		return 0;
		}

		@@ -6065,194 +6069,32 @@ static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
		u32 switch_cfg)
		{
		int port = BP_PORT(bp);
		u32 ext_phy_type;

		switch (switch_cfg) {
		case SWITCH_CFG_1G:
		BNX2X_DEV_INFO("switch_cfg 0x%x (1G)\n", switch_cfg);

		ext_phy_type =
		SERDES_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
		switch (ext_phy_type) {
		case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
		BNX2X_DEV_INFO("ext_phy_type 0x%x (Direct)\n",
		ext_phy_type);

		bp->port.supported \|= (SUPPORTED_10baseT_Half \|
		SUPPORTED_10baseT_Full \|
		SUPPORTED_100baseT_Half \|
		SUPPORTED_100baseT_Full \|
		SUPPORTED_1000baseT_Full \|
		SUPPORTED_2500baseX_Full \|
		SUPPORTED_TP \|
		SUPPORTED_FIBRE \|
		SUPPORTED_Autoneg \|
		SUPPORTED_Pause \|
		SUPPORTED_Asym_Pause);
		bp->port.supported = 0;
		switch (bp->link_params.num_phys) {
		case 1:
		bp->port.supported = bp->link_params.phy[INT_PHY].supported;
		break;

		case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
		BNX2X_DEV_INFO("ext_phy_type 0x%x (5482)\n",
		ext_phy_type);

		bp->port.supported \|= (SUPPORTED_10baseT_Half \|
		SUPPORTED_10baseT_Full \|
		SUPPORTED_100baseT_Half \|
		SUPPORTED_100baseT_Full \|
		SUPPORTED_1000baseT_Full \|
		SUPPORTED_TP \|
		SUPPORTED_FIBRE \|
		SUPPORTED_Autoneg \|
		SUPPORTED_Pause \|
		SUPPORTED_Asym_Pause);
		case 2:
		bp->port.supported = bp->link_params.phy[EXT_PHY1].supported;
		break;
		}

		default:
		BNX2X_ERR("NVRAM config error. "
		"BAD SerDes ext_phy_config 0x%x\n",
		bp->link_params.ext_phy_config);
		if (!(bp->port.supported)) {
		BNX2X_ERR("NVRAM config error. BAD phy config."
		"PHY1 config 0x%x\n",
		SHMEM_RD(bp,
		dev_info.port_hw_config[port].external_phy_config));
		return;
		}

		switch (switch_cfg) {
		case SWITCH_CFG_1G:
		bp->port.phy_addr = REG_RD(bp, NIG_REG_SERDES0_CTRL_PHY_ADDR +
		port*0x10);
		BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
		break;

		case SWITCH_CFG_10G:
		BNX2X_DEV_INFO("switch_cfg 0x%x (10G)\n", switch_cfg);

		ext_phy_type =
		XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
		switch (ext_phy_type) {
		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
		BNX2X_DEV_INFO("ext_phy_type 0x%x (Direct)\n",
		ext_phy_type);

		bp->port.supported \|= (SUPPORTED_10baseT_Half \|
		SUPPORTED_10baseT_Full \|
		SUPPORTED_100baseT_Half \|
		SUPPORTED_100baseT_Full \|
		SUPPORTED_1000baseT_Full \|
		SUPPORTED_2500baseX_Full \|
		SUPPORTED_10000baseT_Full \|
		SUPPORTED_TP \|
		SUPPORTED_FIBRE \|
		SUPPORTED_Autoneg \|
		SUPPORTED_Pause \|
		SUPPORTED_Asym_Pause);
		break;

		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
		BNX2X_DEV_INFO("ext_phy_type 0x%x (8072)\n",
		ext_phy_type);

		bp->port.supported \|= (SUPPORTED_10000baseT_Full \|
		SUPPORTED_1000baseT_Full \|
		SUPPORTED_FIBRE \|
		SUPPORTED_Autoneg \|
		SUPPORTED_Pause \|
		SUPPORTED_Asym_Pause);
		break;

		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
		BNX2X_DEV_INFO("ext_phy_type 0x%x (8073)\n",
		ext_phy_type);

		bp->port.supported \|= (SUPPORTED_10000baseT_Full \|
		SUPPORTED_2500baseX_Full \|
		SUPPORTED_1000baseT_Full \|
		SUPPORTED_FIBRE \|
		SUPPORTED_Autoneg \|
		SUPPORTED_Pause \|
		SUPPORTED_Asym_Pause);
		break;

		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
		BNX2X_DEV_INFO("ext_phy_type 0x%x (8705)\n",
		ext_phy_type);

		bp->port.supported \|= (SUPPORTED_10000baseT_Full \|
		SUPPORTED_FIBRE \|
		SUPPORTED_Pause \|
		SUPPORTED_Asym_Pause);
		break;

		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
		BNX2X_DEV_INFO("ext_phy_type 0x%x (8706)\n",
		ext_phy_type);

		bp->port.supported \|= (SUPPORTED_10000baseT_Full \|
		SUPPORTED_1000baseT_Full \|
		SUPPORTED_FIBRE \|
		SUPPORTED_Pause \|
		SUPPORTED_Asym_Pause);
		break;

		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
		BNX2X_DEV_INFO("ext_phy_type 0x%x (8726)\n",
		ext_phy_type);

		bp->port.supported \|= (SUPPORTED_10000baseT_Full \|
		SUPPORTED_1000baseT_Full \|
		SUPPORTED_Autoneg \|
		SUPPORTED_FIBRE \|
		SUPPORTED_Pause \|
		SUPPORTED_Asym_Pause);
		break;

		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
		BNX2X_DEV_INFO("ext_phy_type 0x%x (8727)\n",
		ext_phy_type);

		bp->port.supported \|= (SUPPORTED_10000baseT_Full \|
		SUPPORTED_1000baseT_Full \|
		SUPPORTED_Autoneg \|
		SUPPORTED_FIBRE \|
		SUPPORTED_Pause \|
		SUPPORTED_Asym_Pause);
		break;

		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
		BNX2X_DEV_INFO("ext_phy_type 0x%x (SFX7101)\n",
		ext_phy_type);

		bp->port.supported \|= (SUPPORTED_10000baseT_Full \|
		SUPPORTED_TP \|
		SUPPORTED_Autoneg \|
		SUPPORTED_Pause \|
		SUPPORTED_Asym_Pause);
		break;

		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
		BNX2X_DEV_INFO("ext_phy_type 0x%x (BCM848xx)\n",
		ext_phy_type);

		bp->port.supported \|= (SUPPORTED_10baseT_Half \|
		SUPPORTED_10baseT_Full \|
		SUPPORTED_100baseT_Half \|
		SUPPORTED_100baseT_Full \|
		SUPPORTED_1000baseT_Full \|
		SUPPORTED_10000baseT_Full \|
		SUPPORTED_TP \|
		SUPPORTED_Autoneg \|
		SUPPORTED_Pause \|
		SUPPORTED_Asym_Pause);
		break;

		case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
		BNX2X_ERR("XGXS PHY Failure detected 0x%x\n",
		bp->link_params.ext_phy_config);
		break;

		default:
		BNX2X_ERR("NVRAM config error. "
		"BAD XGXS ext_phy_config 0x%x\n",
		bp->link_params.ext_phy_config);
		return;
		}

		bp->port.phy_addr = REG_RD(bp, NIG_REG_XGXS0_CTRL_PHY_ADDR +
		port*0x18);
		BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
		@@ -6264,8 +6106,6 @@ static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
		bp->port.link_config);
		return;
		}
		bp->link_params.phy_addr = bp->port.phy_addr;

		/* mask what we support according to speed_cap_mask */
		if (!(bp->link_params.speed_cap_mask &
		PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
		@@ -6309,25 +6149,10 @@ static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
		bp->link_params.req_line_speed = SPEED_AUTO_NEG;
		bp->port.advertising = bp->port.supported;
		} else {
		u32 ext_phy_type =
		XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);

		if ((ext_phy_type ==
		PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) \|\|
		(ext_phy_type ==
		PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706)) {
		/* force 10G, no AN */
		bp->link_params.req_line_speed = SPEED_10000;
		bp->port.advertising =
		(ADVERTISED_10000baseT_Full \|
		bp->port.advertising = (ADVERTISED_10000baseT_Full \|
		ADVERTISED_FIBRE);
		break;
		}
		BNX2X_ERR("NVRAM config error. "
		"Invalid link_config 0x%x"
		" Autoneg not supported\n",
		bp->port.link_config);
		return;
		}
		break;

		@@ -6475,27 +6300,13 @@ static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
		int port = BP_PORT(bp);
		u32 val, val2;
		u32 config;
		u16 i;
		u32 ext_phy_type;
		u32 ext_phy_type, ext_phy_config;;

		bp->link_params.bp = bp;
		bp->link_params.port = port;

		bp->link_params.lane_config =
		SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
		bp->link_params.ext_phy_config =
		SHMEM_RD(bp,
		dev_info.port_hw_config[port].external_phy_config);
		/* BCM8727_NOC => BCM8727 no over current */
		if (XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config) ==
		PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC) {
		bp->link_params.ext_phy_config &=
		~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
		bp->link_params.ext_phy_config \|=
		PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727;
		bp->link_params.feature_config_flags \|=
		FEATURE_CONFIG_BCM8727_NOC;
		}

		bp->link_params.speed_cap_mask =
		SHMEM_RD(bp,
		@@ -6504,18 +6315,6 @@ static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
		bp->port.link_config =
		SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);

		/* Get the 4 lanes xgxs config rx and tx */
		for (i = 0; i < 2; i++) {
		val = SHMEM_RD(bp,
		dev_info.port_hw_config[port].xgxs_config_rx[i<<1]);
		bp->link_params.xgxs_config_rx[i << 1] = ((val>>16) & 0xffff);
		bp->link_params.xgxs_config_rx[(i << 1) + 1] = (val & 0xffff);

		val = SHMEM_RD(bp,
		dev_info.port_hw_config[port].xgxs_config_tx[i<<1]);
		bp->link_params.xgxs_config_tx[i << 1] = ((val>>16) & 0xffff);
		bp->link_params.xgxs_config_tx[(i << 1) + 1] = (val & 0xffff);
		}

		/* If the device is capable of WoL, set the default state according
		* to the HW
		@@ -6524,14 +6323,14 @@ static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
		bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
		(config & PORT_FEATURE_WOL_ENABLED));

		BNX2X_DEV_INFO("lane_config 0x%08x ext_phy_config 0x%08x"
		BNX2X_DEV_INFO("lane_config 0x%08x"
		" speed_cap_mask 0x%08x link_config 0x%08x\n",
		bp->link_params.lane_config,
		bp->link_params.ext_phy_config,
		bp->link_params.speed_cap_mask, bp->port.link_config);

		bp->link_params.switch_cfg \|= (bp->port.link_config &
		PORT_FEATURE_CONNECTED_SWITCH_MASK);
		bnx2x_phy_probe(&bp->link_params);
		bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);

		bnx2x_link_settings_requested(bp);
		@@ -6540,14 +6339,17 @@ static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
		* If connected directly, work with the internal PHY, otherwise, work
		* with the external PHY
		*/
		ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
		ext_phy_config =
		SHMEM_RD(bp,
		dev_info.port_hw_config[port].external_phy_config);
		ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
		if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
		bp->mdio.prtad = bp->link_params.phy_addr;
		bp->mdio.prtad = bp->port.phy_addr;

		else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
		(ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
		bp->mdio.prtad =
		XGXS_EXT_PHY_ADDR(bp->link_params.ext_phy_config);
		XGXS_EXT_PHY_ADDR(ext_phy_config);

		val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
		val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);

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