Commit b770ea52 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'omap-for-v3.8/gpmc-signed' of... 

Merge tag 'omap-for-v3.8/gpmc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers

From Tony Lindgren <tony@atomide.com>:

omap GPMC (General Purpose Memory Controller) updates via Afzal Mohammed <afzal@ti.com>:

These changes provide a generic gpmc timing calculation method,
migrates existing peripherals that makes use of custom gpmc timing
calculation method to use the new generic one.

The generic timing routine has been tested with onenand, smsc911x,
and tusb6010 devices connected to GPMC in addition to simulating
other devices support in the mainline kernel.

* tag 'omap-for-v3.8/gpmc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap

:
  ARM: OMAP2+: tusb6010: generic timing calculation
  ARM: OMAP2+: smc91x: generic timing calculation
  ARM: OMAP2+: onenand: generic timing calculation
  ARM: OMAP2+: gpmc: generic timing calculation
  ARM: OMAP2+: gpmc: handle additional timings
  ARM: OMAP2+: nand: remove redundant rounding

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents cf1fb2df 86983087

Documentation/bus-devices/ti-gpmc.txt

0 → 100644
+122 −0
Original line number Diff line number Diff line 
GPMC (General Purpose Memory Controller):

=========================================



GPMC is an unified memory controller dedicated to interfacing external

memory devices like

 * Asynchronous SRAM like memories and application specific integrated

   circuit devices.

 * Asynchronous, synchronous, and page mode burst NOR flash devices

   NAND flash

 * Pseudo-SRAM devices



GPMC is found on Texas Instruments SoC's (OMAP based)

IP details: http://www.ti.com/lit/pdf/spruh73 section 7.1





GPMC generic timing calculation:

================================



GPMC has certain timings that has to be programmed for proper

functioning of the peripheral, while peripheral has another set of

timings. To have peripheral work with gpmc, peripheral timings has to

be translated to the form gpmc can understand. The way it has to be

translated depends on the connected peripheral. Also there is a

dependency for certain gpmc timings on gpmc clock frequency. Hence a

generic timing routine was developed to achieve above requirements.



Generic routine provides a generic method to calculate gpmc timings

from gpmc peripheral timings. struct gpmc_device_timings fields has to

be updated with timings from the datasheet of the peripheral that is

connected to gpmc. A few of the peripheral timings can be fed either

in time or in cycles, provision to handle this scenario has been

provided (refer struct gpmc_device_timings definition). It may so

happen that timing as specified by peripheral datasheet is not present

in timing structure, in this scenario, try to correlate peripheral

timing to the one available. If that doesn't work, try to add a new

field as required by peripheral, educate generic timing routine to

handle it, make sure that it does not break any of the existing.

Then there may be cases where peripheral datasheet doesn't mention

certain fields of struct gpmc_device_timings, zero those entries.



Generic timing routine has been verified to work properly on

multiple onenand's and tusb6010 peripherals.



A word of caution: generic timing routine has been developed based

on understanding of gpmc timings, peripheral timings, available

custom timing routines, a kind of reverse engineering without

most of the datasheets & hardware (to be exact none of those supported

in mainline having custom timing routine) and by simulation.



gpmc timing dependency on peripheral timings:

[<gpmc_timing>: <peripheral timing1>, <peripheral timing2> ...]



1. common

cs_on: t_ceasu

adv_on: t_avdasu, t_ceavd



2. sync common

sync_clk: clk

page_burst_access: t_bacc

clk_activation: t_ces, t_avds



3. read async muxed

adv_rd_off: t_avdp_r

oe_on: t_oeasu, t_aavdh

access: t_iaa, t_oe, t_ce, t_aa

rd_cycle: t_rd_cycle, t_cez_r, t_oez



4. read async non-muxed

adv_rd_off: t_avdp_r

oe_on: t_oeasu

access: t_iaa, t_oe, t_ce, t_aa

rd_cycle: t_rd_cycle, t_cez_r, t_oez



5. read sync muxed

adv_rd_off: t_avdp_r, t_avdh

oe_on: t_oeasu, t_ach, cyc_aavdh_oe

access: t_iaa, cyc_iaa, cyc_oe

rd_cycle: t_cez_r, t_oez, t_ce_rdyz



6. read sync non-muxed

adv_rd_off: t_avdp_r

oe_on: t_oeasu

access: t_iaa, cyc_iaa, cyc_oe

rd_cycle: t_cez_r, t_oez, t_ce_rdyz



7. write async muxed

adv_wr_off: t_avdp_w

we_on, wr_data_mux_bus: t_weasu, t_aavdh, cyc_aavhd_we

we_off: t_wpl

cs_wr_off: t_wph

wr_cycle: t_cez_w, t_wr_cycle



8. write async non-muxed

adv_wr_off: t_avdp_w

we_on, wr_data_mux_bus: t_weasu

we_off: t_wpl

cs_wr_off: t_wph

wr_cycle: t_cez_w, t_wr_cycle



9. write sync muxed

adv_wr_off: t_avdp_w, t_avdh

we_on, wr_data_mux_bus: t_weasu, t_rdyo, t_aavdh, cyc_aavhd_we

we_off: t_wpl, cyc_wpl

cs_wr_off: t_wph

wr_cycle: t_cez_w, t_ce_rdyz



10. write sync non-muxed

adv_wr_off: t_avdp_w

we_on, wr_data_mux_bus: t_weasu, t_rdyo

we_off: t_wpl, cyc_wpl

cs_wr_off: t_wph

wr_cycle: t_cez_w, t_ce_rdyz





Note: Many of gpmc timings are dependent on other gpmc timings (a few

gpmc timings purely dependent on other gpmc timings, a reason that

some of the gpmc timings are missing above), and it will result in

indirect dependency of peripheral timings to gpmc timings other than

mentioned above, refer timing routine for more details. To know what

these peripheral timings correspond to, please see explanations in

struct gpmc_device_timings definition. And for gpmc timings refer

IP details (link above).

arch/arm/mach-omap2/gpmc-nand.c

+13 −13
Original line number Diff line number Diff line
@@ -52,27 +52,27 @@ static int omap2_nand_gpmc_retime( 


	memset(&t, 0, sizeof(t));

	t.sync_clk = gpmc_t->sync_clk;

	t.cs_on = gpmc_round_ns_to_ticks(gpmc_t->cs_on);

	t.adv_on = gpmc_round_ns_to_ticks(gpmc_t->adv_on);

	t.cs_on = gpmc_t->cs_on;

	t.adv_on = gpmc_t->adv_on;



	/* Read */

	t.adv_rd_off = gpmc_round_ns_to_ticks(gpmc_t->adv_rd_off);

	t.adv_rd_off = gpmc_t->adv_rd_off;

	t.oe_on  = t.adv_on;

	t.access = gpmc_round_ns_to_ticks(gpmc_t->access);

	t.oe_off = gpmc_round_ns_to_ticks(gpmc_t->oe_off);

	t.cs_rd_off = gpmc_round_ns_to_ticks(gpmc_t->cs_rd_off);

	t.rd_cycle  = gpmc_round_ns_to_ticks(gpmc_t->rd_cycle);

	t.access = gpmc_t->access;

	t.oe_off = gpmc_t->oe_off;

	t.cs_rd_off = gpmc_t->cs_rd_off;

	t.rd_cycle = gpmc_t->rd_cycle;



	/* Write */

	t.adv_wr_off = gpmc_round_ns_to_ticks(gpmc_t->adv_wr_off);

	t.adv_wr_off = gpmc_t->adv_wr_off;

	t.we_on  = t.oe_on;

	if (cpu_is_omap34xx()) {

	    t.wr_data_mux_bus =	gpmc_round_ns_to_ticks(gpmc_t->wr_data_mux_bus);

	    t.wr_access = gpmc_round_ns_to_ticks(gpmc_t->wr_access);

		t.wr_data_mux_bus = gpmc_t->wr_data_mux_bus;

		t.wr_access = gpmc_t->wr_access;

	}

	t.we_off = gpmc_round_ns_to_ticks(gpmc_t->we_off);

	t.cs_wr_off = gpmc_round_ns_to_ticks(gpmc_t->cs_wr_off);

	t.wr_cycle  = gpmc_round_ns_to_ticks(gpmc_t->wr_cycle);

	t.we_off = gpmc_t->we_off;

	t.cs_wr_off = gpmc_t->cs_wr_off;

	t.wr_cycle = gpmc_t->wr_cycle;



	/* Configure GPMC */

	if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)

arch/arm/mach-omap2/gpmc-onenand.c

+43 −100
Original line number Diff line number Diff line
@@ -33,7 +33,6 @@ 


static unsigned onenand_flags;

static unsigned latency;

static int fclk_offset;



static struct omap_onenand_platform_data *gpmc_onenand_data;
@@ -50,6 +49,7 @@ static struct platform_device gpmc_onenand_device = { 


static struct gpmc_timings omap2_onenand_calc_async_timings(void)

{

	struct gpmc_device_timings dev_t;

	struct gpmc_timings t;



	const int t_cer = 15;
@@ -59,35 +59,24 @@ static struct gpmc_timings omap2_onenand_calc_async_timings(void) 
	const int t_aa = 76;

	const int t_oe = 20;

	const int t_cez = 20; /* max of t_cez, t_oez */

	const int t_ds = 30;

	const int t_wpl = 40;

	const int t_wph = 30;



	memset(&t, 0, sizeof(t));

	t.sync_clk = 0;

	t.cs_on = 0;

	t.adv_on = 0;



	/* Read */

	t.adv_rd_off = gpmc_round_ns_to_ticks(max_t(int, t_avdp, t_cer));

	t.oe_on  = t.adv_rd_off + gpmc_round_ns_to_ticks(t_aavdh);

	t.access = t.adv_on + gpmc_round_ns_to_ticks(t_aa);

	t.access = max_t(int, t.access, t.cs_on + gpmc_round_ns_to_ticks(t_ce));

	t.access = max_t(int, t.access, t.oe_on + gpmc_round_ns_to_ticks(t_oe));

	t.oe_off = t.access + gpmc_round_ns_to_ticks(1);

	t.cs_rd_off = t.oe_off;

	t.rd_cycle  = t.cs_rd_off + gpmc_round_ns_to_ticks(t_cez);



	/* Write */

	t.adv_wr_off = t.adv_rd_off;

	t.we_on  = t.oe_on;

	if (cpu_is_omap34xx()) {

		t.wr_data_mux_bus = t.we_on;

		t.wr_access = t.we_on + gpmc_round_ns_to_ticks(t_ds);

	}

	t.we_off = t.we_on + gpmc_round_ns_to_ticks(t_wpl);

	t.cs_wr_off = t.we_off + gpmc_round_ns_to_ticks(t_wph);

	t.wr_cycle  = t.cs_wr_off + gpmc_round_ns_to_ticks(t_cez);

	memset(&dev_t, 0, sizeof(dev_t));



	dev_t.mux = true;

	dev_t.t_avdp_r = max_t(int, t_avdp, t_cer) * 1000;

	dev_t.t_avdp_w = dev_t.t_avdp_r;

	dev_t.t_aavdh = t_aavdh * 1000;

	dev_t.t_aa = t_aa * 1000;

	dev_t.t_ce = t_ce * 1000;

	dev_t.t_oe = t_oe * 1000;

	dev_t.t_cez_r = t_cez * 1000;

	dev_t.t_cez_w = dev_t.t_cez_r;

	dev_t.t_wpl = t_wpl * 1000;

	dev_t.t_wph = t_wph * 1000;



	gpmc_calc_timings(&t, &dev_t);



	return t;

}
@@ -173,18 +162,15 @@ static struct gpmc_timings 
omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg,

				int freq)

{

	struct gpmc_device_timings dev_t;

	struct gpmc_timings t;

	const int t_cer  = 15;

	const int t_avdp = 12;

	const int t_cez  = 20; /* max of t_cez, t_oez */

	const int t_ds   = 30;

	const int t_wpl  = 40;

	const int t_wph  = 30;

	int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;

	u32 reg;

	int div, fclk_offset_ns, gpmc_clk_ns;

	int ticks_cez;

	int cs = cfg->cs;

	int div, gpmc_clk_ns;



	if (cfg->flags & ONENAND_SYNC_READ)

		onenand_flags = ONENAND_FLAG_SYNCREAD;
@@ -251,77 +237,35 @@ omap2_onenand_calc_sync_timings(struct omap_onenand_platform_data *cfg, 
		latency = 4;



	/* Set synchronous read timings */

	memset(&t, 0, sizeof(t));



	if (div == 1) {

		reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2);

		reg |= (1 << 7);

		gpmc_cs_write_reg(cs, GPMC_CS_CONFIG2, reg);

		reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG3);

		reg |= (1 << 7);

		gpmc_cs_write_reg(cs, GPMC_CS_CONFIG3, reg);

		reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG4);

		reg |= (1 << 7);

		reg |= (1 << 23);

		gpmc_cs_write_reg(cs, GPMC_CS_CONFIG4, reg);

	} else {

		reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2);

		reg &= ~(1 << 7);

		gpmc_cs_write_reg(cs, GPMC_CS_CONFIG2, reg);

		reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG3);

		reg &= ~(1 << 7);

		gpmc_cs_write_reg(cs, GPMC_CS_CONFIG3, reg);

		reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG4);

		reg &= ~(1 << 7);

		reg &= ~(1 << 23);

		gpmc_cs_write_reg(cs, GPMC_CS_CONFIG4, reg);

	}

	memset(&dev_t, 0, sizeof(dev_t));



	t.sync_clk = min_gpmc_clk_period;

	t.cs_on = 0;

	t.adv_on = 0;

	fclk_offset_ns = gpmc_round_ns_to_ticks(max_t(int, t_ces, t_avds));

	fclk_offset = gpmc_ns_to_ticks(fclk_offset_ns);

	t.page_burst_access = gpmc_clk_ns;



	/* Read */

	t.adv_rd_off = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_avdh));

	t.oe_on = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_ach));

	/* Force at least 1 clk between AVD High to OE Low */

	if (t.oe_on <= t.adv_rd_off)

		t.oe_on = t.adv_rd_off + gpmc_round_ns_to_ticks(1);

	t.access = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div);

	t.oe_off = t.access + gpmc_round_ns_to_ticks(1);

	t.cs_rd_off = t.oe_off;

	ticks_cez = ((gpmc_ns_to_ticks(t_cez) + div - 1) / div) * div;

	t.rd_cycle = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div +

		     ticks_cez);



	/* Write */

	dev_t.mux = true;

	dev_t.sync_read = true;

	if (onenand_flags & ONENAND_FLAG_SYNCWRITE) {

		t.adv_wr_off = t.adv_rd_off;

		t.we_on  = 0;

		t.we_off = t.cs_rd_off;

		t.cs_wr_off = t.cs_rd_off;

		t.wr_cycle  = t.rd_cycle;

		if (cpu_is_omap34xx()) {

			t.wr_data_mux_bus = gpmc_ticks_to_ns(fclk_offset +

					gpmc_ps_to_ticks(min_gpmc_clk_period +

					t_rdyo * 1000));

			t.wr_access = t.access;

		}

		dev_t.sync_write = true;

	} else {

		t.adv_wr_off = gpmc_round_ns_to_ticks(max_t(int,

							t_avdp, t_cer));

		t.we_on  = t.adv_wr_off + gpmc_round_ns_to_ticks(t_aavdh);

		t.we_off = t.we_on + gpmc_round_ns_to_ticks(t_wpl);

		t.cs_wr_off = t.we_off + gpmc_round_ns_to_ticks(t_wph);

		t.wr_cycle  = t.cs_wr_off + gpmc_round_ns_to_ticks(t_cez);

		if (cpu_is_omap34xx()) {

			t.wr_data_mux_bus = t.we_on;

			t.wr_access = t.we_on + gpmc_round_ns_to_ticks(t_ds);

		}

		dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;

		dev_t.t_wpl = t_wpl * 1000;

		dev_t.t_wph = t_wph * 1000;

		dev_t.t_aavdh = t_aavdh * 1000;

	}

	dev_t.ce_xdelay = true;

	dev_t.avd_xdelay = true;

	dev_t.oe_xdelay = true;

	dev_t.we_xdelay = true;

	dev_t.clk = min_gpmc_clk_period;

	dev_t.t_bacc = dev_t.clk;

	dev_t.t_ces = t_ces * 1000;

	dev_t.t_avds = t_avds * 1000;

	dev_t.t_avdh = t_avdh * 1000;

	dev_t.t_ach = t_ach * 1000;

	dev_t.cyc_iaa = (latency + 1);

	dev_t.t_cez_r = t_cez * 1000;

	dev_t.t_cez_w = dev_t.t_cez_r;

	dev_t.cyc_aavdh_oe = 1;

	dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;



	gpmc_calc_timings(&t, &dev_t);



	return t;

}
@@ -338,7 +282,6 @@ static int gpmc_set_sync_mode(int cs, struct gpmc_timings *t) 
			  (sync_read ? GPMC_CONFIG1_READTYPE_SYNC : 0) |

			  (sync_write ? GPMC_CONFIG1_WRITEMULTIPLE_SUPP : 0) |

			  (sync_write ? GPMC_CONFIG1_WRITETYPE_SYNC : 0) |

			  GPMC_CONFIG1_CLKACTIVATIONTIME(fclk_offset) |

			  GPMC_CONFIG1_PAGE_LEN(2) |

			  (cpu_is_omap34xx() ? 0 :

				(GPMC_CONFIG1_WAIT_READ_MON |

arch/arm/mach-omap2/gpmc-smc91x.c

+17 −26
Original line number Diff line number Diff line
@@ -58,6 +58,7 @@ static struct platform_device gpmc_smc91x_device = { 
static int smc91c96_gpmc_retime(void)

{

	struct gpmc_timings t;

	struct gpmc_device_timings dev_t;

	const int t3 = 10;	/* Figure 12.2 read and 12.4 write */

	const int t4_r = 20;	/* Figure 12.2 read */

	const int t4_w = 5;	/* Figure 12.4 write */
@@ -68,32 +69,6 @@ static int smc91c96_gpmc_retime(void) 
	const int t20 = 185;	/* Figure 12.2 read and 12.4 write */

	u32 l;



	memset(&t, 0, sizeof(t));



	/* Read timings */

	t.cs_on = 0;

	t.adv_on = t.cs_on;

	t.oe_on = t.adv_on + t3;

	t.access = t.oe_on + t5;

	t.oe_off = t.access;

	t.adv_rd_off = t.oe_off + max(t4_r, t6);

	t.cs_rd_off = t.oe_off;

	t.rd_cycle = t20 - t.oe_on;



	/* Write timings */

	t.we_on = t.adv_on + t3;



	if (cpu_is_omap34xx() && (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)) {

		t.wr_data_mux_bus = t.we_on;

		t.we_off = t.wr_data_mux_bus + t7;

	} else

		t.we_off = t.we_on + t7;

	if (cpu_is_omap34xx())

		t.wr_access = t.we_off;

	t.adv_wr_off = t.we_off + max(t4_w, t8);

	t.cs_wr_off = t.we_off + t4_w;

	t.wr_cycle = t20 - t.we_on;



	l = GPMC_CONFIG1_DEVICESIZE_16;

	if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)

		l |= GPMC_CONFIG1_MUXADDDATA;
@@ -115,6 +90,22 @@ static int smc91c96_gpmc_retime(void) 
	if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)

		return 0;



	memset(&dev_t, 0, sizeof(dev_t));



	dev_t.t_oeasu = t3 * 1000;

	dev_t.t_oe = t5 * 1000;

	dev_t.t_cez_r = t4_r * 1000;

	dev_t.t_oez = t6 * 1000;

	dev_t.t_rd_cycle = (t20 - t3) * 1000;



	dev_t.t_weasu = t3 * 1000;

	dev_t.t_wpl = t7 * 1000;

	dev_t.t_wph = t8 * 1000;

	dev_t.t_cez_w = t4_w * 1000;

	dev_t.t_wr_cycle = (t20 - t3) * 1000;



	gpmc_calc_timings(&t, &dev_t);



	return gpmc_cs_set_timings(gpmc_cfg->cs, &t);

}

arch/arm/mach-omap2/gpmc.c

+373 −0
Original line number Diff line number Diff line
@@ -74,6 +74,13 @@ 
#define GPMC_ECC_CTRL_ECCREG8		0x008

#define GPMC_ECC_CTRL_ECCREG9		0x009



#define	GPMC_CONFIG2_CSEXTRADELAY		BIT(7)

#define	GPMC_CONFIG3_ADVEXTRADELAY		BIT(7)

#define	GPMC_CONFIG4_OEEXTRADELAY		BIT(7)

#define	GPMC_CONFIG4_WEEXTRADELAY		BIT(23)

#define	GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN	BIT(6)

#define	GPMC_CONFIG6_CYCLE2CYCLESAMECSEN	BIT(7)



#define GPMC_CS0_OFFSET		0x60

#define GPMC_CS_SIZE		0x30

#define	GPMC_BCH_SIZE		0x10
@@ -223,6 +230,51 @@ unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns) 
	return ticks * gpmc_get_fclk_period() / 1000;

}



static unsigned int gpmc_ticks_to_ps(unsigned int ticks)

{

	return ticks * gpmc_get_fclk_period();

}



static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)

{

	unsigned long ticks = gpmc_ps_to_ticks(time_ps);



	return ticks * gpmc_get_fclk_period();

}



static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)

{

	u32 l;



	l = gpmc_cs_read_reg(cs, reg);

	if (value)

		l |= mask;

	else

		l &= ~mask;

	gpmc_cs_write_reg(cs, reg, l);

}



static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)

{

	gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,

			   GPMC_CONFIG1_TIME_PARA_GRAN,

			   p->time_para_granularity);

	gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,

			   GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);

	gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,

			   GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);

	gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,

			   GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);

	gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,

			   GPMC_CONFIG4_OEEXTRADELAY, p->we_extra_delay);

	gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,

			   GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,

			   p->cycle2cyclesamecsen);

	gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,

			   GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,

			   p->cycle2cyclediffcsen);

}



#ifdef DEBUG

static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,

			       int time, const char *name)
@@ -316,6 +368,12 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t) 


	GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);



	GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround);

	GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay);



	GPMC_SET_ONE(GPMC_CS_CONFIG1, 18, 19, wait_monitoring);

	GPMC_SET_ONE(GPMC_CS_CONFIG1, 25, 26, clk_activation);



	if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)

		GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);

	if (gpmc_capability & GPMC_HAS_WR_ACCESS)
@@ -335,6 +393,8 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t) 
		gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);

	}



	gpmc_cs_bool_timings(cs, &t->bool_timings);



	return 0;

}
@@ -748,6 +808,319 @@ static int __devinit gpmc_mem_init(void) 
	return 0;

}



static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)

{

	u32 temp;

	int div;



	div = gpmc_calc_divider(sync_clk);

	temp = gpmc_ps_to_ticks(time_ps);

	temp = (temp + div - 1) / div;

	return gpmc_ticks_to_ps(temp * div);

}



/* XXX: can the cycles be avoided ? */

static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,

				struct gpmc_device_timings *dev_t)

{

	bool mux = dev_t->mux;

	u32 temp;



	/* adv_rd_off */

	temp = dev_t->t_avdp_r;

	/* XXX: mux check required ? */

	if (mux) {

		/* XXX: t_avdp not to be required for sync, only added for tusb

		 * this indirectly necessitates requirement of t_avdp_r and

		 * t_avdp_w instead of having a single t_avdp

		 */

		temp = max_t(u32, temp,	gpmc_t->clk_activation + dev_t->t_avdh);

		temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);

	}

	gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);



	/* oe_on */

	temp = dev_t->t_oeasu; /* XXX: remove this ? */

	if (mux) {

		temp = max_t(u32, temp,	gpmc_t->clk_activation + dev_t->t_ach);

		temp = max_t(u32, temp, gpmc_t->adv_rd_off +

				gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));

	}

	gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);



	/* access */

	/* XXX: any scope for improvement ?, by combining oe_on

	 * and clk_activation, need to check whether

	 * access = clk_activation + round to sync clk ?

	 */

	temp = max_t(u32, dev_t->t_iaa,	dev_t->cyc_iaa * gpmc_t->sync_clk);

	temp += gpmc_t->clk_activation;

	if (dev_t->cyc_oe)

		temp = max_t(u32, temp, gpmc_t->oe_on +

				gpmc_ticks_to_ps(dev_t->cyc_oe));

	gpmc_t->access = gpmc_round_ps_to_ticks(temp);



	gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);

	gpmc_t->cs_rd_off = gpmc_t->oe_off;



	/* rd_cycle */

	temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);

	temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +

							gpmc_t->access;

	/* XXX: barter t_ce_rdyz with t_cez_r ? */

	if (dev_t->t_ce_rdyz)

		temp = max_t(u32, temp,	gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);

	gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);



	return 0;

}



static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,

				struct gpmc_device_timings *dev_t)

{

	bool mux = dev_t->mux;

	u32 temp;



	/* adv_wr_off */

	temp = dev_t->t_avdp_w;

	if (mux) {

		temp = max_t(u32, temp,

			gpmc_t->clk_activation + dev_t->t_avdh);

		temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);

	}

	gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);



	/* wr_data_mux_bus */

	temp = max_t(u32, dev_t->t_weasu,

			gpmc_t->clk_activation + dev_t->t_rdyo);

	/* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,

	 * and in that case remember to handle we_on properly

	 */

	if (mux) {

		temp = max_t(u32, temp,

			gpmc_t->adv_wr_off + dev_t->t_aavdh);

		temp = max_t(u32, temp, gpmc_t->adv_wr_off +

				gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));

	}

	gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);



	/* we_on */

	if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)

		gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);

	else

		gpmc_t->we_on = gpmc_t->wr_data_mux_bus;



	/* wr_access */

	/* XXX: gpmc_capability check reqd ? , even if not, will not harm */

	gpmc_t->wr_access = gpmc_t->access;



	/* we_off */

	temp = gpmc_t->we_on + dev_t->t_wpl;

	temp = max_t(u32, temp,

			gpmc_t->wr_access + gpmc_ticks_to_ps(1));

	temp = max_t(u32, temp,

		gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));

	gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);



	gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +

							dev_t->t_wph);



	/* wr_cycle */

	temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);

	temp += gpmc_t->wr_access;

	/* XXX: barter t_ce_rdyz with t_cez_w ? */

	if (dev_t->t_ce_rdyz)

		temp = max_t(u32, temp,

				 gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);

	gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);



	return 0;

}



static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,

				struct gpmc_device_timings *dev_t)

{

	bool mux = dev_t->mux;

	u32 temp;



	/* adv_rd_off */

	temp = dev_t->t_avdp_r;

	if (mux)

		temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);

	gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);



	/* oe_on */

	temp = dev_t->t_oeasu;

	if (mux)

		temp = max_t(u32, temp,

			gpmc_t->adv_rd_off + dev_t->t_aavdh);

	gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);



	/* access */

	temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */

				gpmc_t->oe_on + dev_t->t_oe);

	temp = max_t(u32, temp,

				gpmc_t->cs_on + dev_t->t_ce);

	temp = max_t(u32, temp,

				gpmc_t->adv_on + dev_t->t_aa);

	gpmc_t->access = gpmc_round_ps_to_ticks(temp);



	gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);

	gpmc_t->cs_rd_off = gpmc_t->oe_off;



	/* rd_cycle */

	temp = max_t(u32, dev_t->t_rd_cycle,

			gpmc_t->cs_rd_off + dev_t->t_cez_r);

	temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);

	gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);



	return 0;

}



static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,

				struct gpmc_device_timings *dev_t)

{

	bool mux = dev_t->mux;

	u32 temp;



	/* adv_wr_off */

	temp = dev_t->t_avdp_w;

	if (mux)

		temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);

	gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);



	/* wr_data_mux_bus */

	temp = dev_t->t_weasu;

	if (mux) {

		temp = max_t(u32, temp,	gpmc_t->adv_wr_off + dev_t->t_aavdh);

		temp = max_t(u32, temp, gpmc_t->adv_wr_off +

				gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));

	}

	gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);



	/* we_on */

	if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)

		gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);

	else

		gpmc_t->we_on = gpmc_t->wr_data_mux_bus;



	/* we_off */

	temp = gpmc_t->we_on + dev_t->t_wpl;

	gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);



	gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +

							dev_t->t_wph);



	/* wr_cycle */

	temp = max_t(u32, dev_t->t_wr_cycle,

				gpmc_t->cs_wr_off + dev_t->t_cez_w);

	gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);



	return 0;

}



static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,

			struct gpmc_device_timings *dev_t)

{

	u32 temp;



	gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *

						gpmc_get_fclk_period();



	gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(

					dev_t->t_bacc,

					gpmc_t->sync_clk);



	temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);

	gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);



	if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)

		return 0;



	if (dev_t->ce_xdelay)

		gpmc_t->bool_timings.cs_extra_delay = true;

	if (dev_t->avd_xdelay)

		gpmc_t->bool_timings.adv_extra_delay = true;

	if (dev_t->oe_xdelay)

		gpmc_t->bool_timings.oe_extra_delay = true;

	if (dev_t->we_xdelay)

		gpmc_t->bool_timings.we_extra_delay = true;



	return 0;

}



static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,

			struct gpmc_device_timings *dev_t)

{

	u32 temp;



	/* cs_on */

	gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);



	/* adv_on */

	temp = dev_t->t_avdasu;

	if (dev_t->t_ce_avd)

		temp = max_t(u32, temp,

				gpmc_t->cs_on + dev_t->t_ce_avd);

	gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);



	if (dev_t->sync_write || dev_t->sync_read)

		gpmc_calc_sync_common_timings(gpmc_t, dev_t);



	return 0;

}



/* TODO: remove this function once all peripherals are confirmed to

 * work with generic timing. Simultaneously gpmc_cs_set_timings()

 * has to be modified to handle timings in ps instead of ns

*/

static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)

{

	t->cs_on /= 1000;

	t->cs_rd_off /= 1000;

	t->cs_wr_off /= 1000;

	t->adv_on /= 1000;

	t->adv_rd_off /= 1000;

	t->adv_wr_off /= 1000;

	t->we_on /= 1000;

	t->we_off /= 1000;

	t->oe_on /= 1000;

	t->oe_off /= 1000;

	t->page_burst_access /= 1000;

	t->access /= 1000;

	t->rd_cycle /= 1000;

	t->wr_cycle /= 1000;

	t->bus_turnaround /= 1000;

	t->cycle2cycle_delay /= 1000;

	t->wait_monitoring /= 1000;

	t->clk_activation /= 1000;

	t->wr_access /= 1000;

	t->wr_data_mux_bus /= 1000;

}



int gpmc_calc_timings(struct gpmc_timings *gpmc_t,

			struct gpmc_device_timings *dev_t)

{

	memset(gpmc_t, 0, sizeof(*gpmc_t));



	gpmc_calc_common_timings(gpmc_t, dev_t);



	if (dev_t->sync_read)

		gpmc_calc_sync_read_timings(gpmc_t, dev_t);

	else

		gpmc_calc_async_read_timings(gpmc_t, dev_t);



	if (dev_t->sync_write)

		gpmc_calc_sync_write_timings(gpmc_t, dev_t);

	else

		gpmc_calc_async_write_timings(gpmc_t, dev_t);



	/* TODO: remove, see function definition */

	gpmc_convert_ps_to_ns(gpmc_t);



	return 0;

}



static __devinit int gpmc_probe(struct platform_device *pdev)

{

	int rc;

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