Commit b7574a22 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull arm-soc soc updates from Olof Johansson:
 "This is the second batch of SoC updates for the 3.6 merge window,
  containing parts that arrived close to the merge window opening and
  thus needed to sit in linux-next for a while.

  Most contents is updates of Renesas shmobile, with a couple of Samsung
  Exynos patches in the mix."

* tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (39 commits)
  ARM: S3C64XX: Add header file protection macros in pm-core.h
  [CPUFREQ] EXYNOS5250: Add support max 1.7GHz for EXYNOS5250
  ARM: EXYNOS: Add G2D related clock entries for SMDK4X12
  ARM: EXYNOS: Move G2D clock entries to clock-exynos4210.c file
  ARM: shmobile: Fix build problem in pm-sh7372.c for unusual .config
  ARM: shmobile: Take cpuidle dependencies into account correctly
  ARM: mach-shmobile: sh7377 generic board support via DT
  ARM: mach-shmobile: r8a7740 generic board support via DT
  ARM: shmobile: sh7372: completely switch over to using pm-rmobile API
  ARM: shmobile: ap4evb: switch to using pm-rmobile API
  ARM: shmobile: mackerel: switch to using pm-rmobile API
  ARM: shmobile: sh7372: add pm-rmobile domain support
  ARM: shmobile: r8a7740: add A4LC pm domain support
  ARM: shmobile: r8a7740: add A3SP pm domain support
  ARM: shmobile: r8a7740: add A4S pm domain support
  ARM: shmobile: r8a7740: fixup: MSEL1CR 7bit control
  ARM: shmobile: soc-core: add R-mobile PM domain common APIs
  ARM: shmobile: sh7372 A3SM CPUIdle support
  ARM: shmobile: Use INTCA with sh7372 A3SM power domain
  ARM: mach-shmobile: Convert sh_clk_mstp32_register to sh_clk_mstp_register
  ...
parents 148b729b 537cd80c

arch/arm/boot/dts/r8a7740.dtsi

0 → 100644
+21 −0
Original line number Diff line number Diff line 
/*

 * Device Tree Source for the r8a7740 SoC

 *

 * Copyright (C) 2012 Renesas Solutions Corp.

 *

 * This file is licensed under the terms of the GNU General Public License

 * version 2.  This program is licensed "as is" without any warranty of any

 * kind, whether express or implied.

 */



/include/ "skeleton.dtsi"



/ {

	compatible = "renesas,r8a7740";



	cpus {

		cpu@0 {

			compatible = "arm,cortex-a9";

		};

	};

};

arch/arm/boot/dts/sh7377.dtsi

0 → 100644
+21 −0
Original line number Diff line number Diff line 
/*

 * Device Tree Source for the sh7377 SoC

 *

 * Copyright (C) 2012 Renesas Solutions Corp.

 *

 * This file is licensed under the terms of the GNU General Public License

 * version 2.  This program is licensed "as is" without any warranty of any

 * kind, whether express or implied.

 */



/include/ "skeleton.dtsi"



/ {

	compatible = "renesas,sh7377";



	cpus {

		cpu@0 {

			compatible = "arm,cortex-a8";

		};

	};

};

arch/arm/mach-exynos/clock-exynos4.c

+2 −39
Original line number Diff line number Diff line
@@ -619,10 +619,6 @@ static struct clk exynos4_init_clocks_off[] = { 
		.devname	= "samsung-ac97",

		.enable		= exynos4_clk_ip_peril_ctrl,

		.ctrlbit	= (1 << 27),

	}, {

		.name		= "fimg2d",

		.enable		= exynos4_clk_ip_image_ctrl,

		.ctrlbit	= (1 << 0),

	}, {

		.name		= "mfc",

		.devname	= "s5p-mfc",
@@ -819,47 +815,21 @@ static struct clk *exynos4_clkset_mout_g2d0_list[] = { 
	[1] = &exynos4_clk_sclk_apll.clk,

};



static struct clksrc_sources exynos4_clkset_mout_g2d0 = {

struct clksrc_sources exynos4_clkset_mout_g2d0 = {

	.sources	= exynos4_clkset_mout_g2d0_list,

	.nr_sources	= ARRAY_SIZE(exynos4_clkset_mout_g2d0_list),

};



static struct clksrc_clk exynos4_clk_mout_g2d0 = {

	.clk	= {

		.name		= "mout_g2d0",

	},

	.sources = &exynos4_clkset_mout_g2d0,

	.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },

};



static struct clk *exynos4_clkset_mout_g2d1_list[] = {

	[0] = &exynos4_clk_mout_epll.clk,

	[1] = &exynos4_clk_sclk_vpll.clk,

};



static struct clksrc_sources exynos4_clkset_mout_g2d1 = {

struct clksrc_sources exynos4_clkset_mout_g2d1 = {

	.sources	= exynos4_clkset_mout_g2d1_list,

	.nr_sources	= ARRAY_SIZE(exynos4_clkset_mout_g2d1_list),

};



static struct clksrc_clk exynos4_clk_mout_g2d1 = {

	.clk	= {

		.name		= "mout_g2d1",

	},

	.sources = &exynos4_clkset_mout_g2d1,

	.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },

};



static struct clk *exynos4_clkset_mout_g2d_list[] = {

	[0] = &exynos4_clk_mout_g2d0.clk,

	[1] = &exynos4_clk_mout_g2d1.clk,

};



static struct clksrc_sources exynos4_clkset_mout_g2d = {

	.sources	= exynos4_clkset_mout_g2d_list,

	.nr_sources	= ARRAY_SIZE(exynos4_clkset_mout_g2d_list),

};



static struct clk *exynos4_clkset_mout_mfc0_list[] = {

	[0] = &exynos4_clk_mout_mpll.clk,

	[1] = &exynos4_clk_sclk_apll.clk,
@@ -1124,13 +1094,6 @@ static struct clksrc_clk exynos4_clksrcs[] = { 
		.sources = &exynos4_clkset_group,

		.reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 },

		.reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 },

	}, {

		.clk	= {

			.name		= "sclk_fimg2d",

		},

		.sources = &exynos4_clkset_mout_g2d,

		.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },

		.reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },

	}, {

		.clk	= {

			.name		= "sclk_mfc",

arch/arm/mach-exynos/clock-exynos4.h

+3 −0
Original line number Diff line number Diff line
@@ -23,6 +23,9 @@ extern struct clksrc_sources exynos4_clkset_group; 
extern struct clk *exynos4_clkset_aclk_top_list[];

extern struct clk *exynos4_clkset_group_list[];



extern struct clksrc_sources exynos4_clkset_mout_g2d0;

extern struct clksrc_sources exynos4_clkset_mout_g2d1;



extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);

extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);

extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);

arch/arm/mach-exynos/clock-exynos4210.c

+37 −0
Original line number Diff line number Diff line
@@ -48,6 +48,32 @@ static struct clksrc_clk *sysclks[] = { 
	/* nothing here yet */

};



static struct clksrc_clk exynos4210_clk_mout_g2d0 = {

	.clk	= {

		.name		= "mout_g2d0",

	},

	.sources = &exynos4_clkset_mout_g2d0,

	.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },

};



static struct clksrc_clk exynos4210_clk_mout_g2d1 = {

	.clk	= {

		.name		= "mout_g2d1",

	},

	.sources = &exynos4_clkset_mout_g2d1,

	.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },

};



static struct clk *exynos4210_clkset_mout_g2d_list[] = {

	[0] = &exynos4210_clk_mout_g2d0.clk,

	[1] = &exynos4210_clk_mout_g2d1.clk,

};



static struct clksrc_sources exynos4210_clkset_mout_g2d = {

	.sources	= exynos4210_clkset_mout_g2d_list,

	.nr_sources	= ARRAY_SIZE(exynos4210_clkset_mout_g2d_list),

};



static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)

{

	return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable);
@@ -74,6 +100,13 @@ static struct clksrc_clk clksrcs[] = { 
		.sources = &exynos4_clkset_group,

		.reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },

		.reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },

	}, {

		.clk	= {

			.name		= "sclk_fimg2d",

		},

		.sources = &exynos4210_clkset_mout_g2d,

		.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },

		.reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },

	},

};
@@ -105,6 +138,10 @@ static struct clk init_clocks_off[] = { 
		.devname	= SYSMMU_CLOCK_DEVNAME(fimd1, 11),

		.enable		= exynos4_clk_ip_lcd1_ctrl,

		.ctrlbit	= (1 << 4),

	}, {

		.name		= "fimg2d",

		.enable		= exynos4_clk_ip_image_ctrl,

		.ctrlbit	= (1 << 0),

	},

};

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