Commit b74d402e authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'sja1105-cleanups'



Vladimir Oltean says:

====================
SJA1105 DSA coding style cleanup

This series provides some mechanical cleanup patches related to function
names and prototypes.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 5cf37738 1bd44870
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+7 −9
Original line number Diff line number Diff line
@@ -127,15 +127,13 @@ typedef enum {
int sja1105_static_config_reload(struct sja1105_private *priv);

/* From sja1105_spi.c */
int sja1105_spi_send_packed_buf(const struct sja1105_private *priv,
int sja1105_xfer_buf(const struct sja1105_private *priv,
		     sja1105_spi_rw_mode_t rw, u64 reg_addr,
		     void *packed_buf, size_t size_bytes);
int sja1105_spi_send_int(const struct sja1105_private *priv,
			 sja1105_spi_rw_mode_t rw, u64 reg_addr,
			 u64 *value, u64 size_bytes);
int sja1105_spi_send_long_packed_buf(const struct sja1105_private *priv,
				     sja1105_spi_rw_mode_t rw, u64 base_addr,
				     void *packed_buf, u64 buf_len);
int sja1105_xfer_u32(const struct sja1105_private *priv,
		     sja1105_spi_rw_mode_t rw, u64 reg_addr, u32 *value);
int sja1105_xfer_u64(const struct sja1105_private *priv,
		     sja1105_spi_rw_mode_t rw, u64 reg_addr, u64 *value);
int sja1105_static_config_upload(struct sja1105_private *priv);
int sja1105_inhibit_tx(const struct sja1105_private *priv,
		       unsigned long port_bitmap, bool tx_inhibited);
+27 −38
Original line number Diff line number Diff line
@@ -118,9 +118,8 @@ static int sja1105_cgu_idiv_config(struct sja1105_private *priv, int port,
	idiv.pd        = enabled ? 0 : 1; /* Power down? */
	sja1105_cgu_idiv_packing(packed_buf, &idiv, PACK);

	return sja1105_spi_send_packed_buf(priv, SPI_WRITE,
					   regs->cgu_idiv[port], packed_buf,
					   SJA1105_SIZE_CGU_CMD);
	return sja1105_xfer_buf(priv, SPI_WRITE, regs->cgu_idiv[port],
				packed_buf, SJA1105_SIZE_CGU_CMD);
}

static void
@@ -167,9 +166,8 @@ static int sja1105_cgu_mii_tx_clk_config(struct sja1105_private *priv,
	mii_tx_clk.pd        = 0;  /* Power Down off => enabled */
	sja1105_cgu_mii_control_packing(packed_buf, &mii_tx_clk, PACK);

	return sja1105_spi_send_packed_buf(priv, SPI_WRITE,
					   regs->mii_tx_clk[port], packed_buf,
					   SJA1105_SIZE_CGU_CMD);
	return sja1105_xfer_buf(priv, SPI_WRITE, regs->mii_tx_clk[port],
				packed_buf, SJA1105_SIZE_CGU_CMD);
}

static int
@@ -192,9 +190,8 @@ sja1105_cgu_mii_rx_clk_config(struct sja1105_private *priv, int port)
	mii_rx_clk.pd        = 0;  /* Power Down off => enabled */
	sja1105_cgu_mii_control_packing(packed_buf, &mii_rx_clk, PACK);

	return sja1105_spi_send_packed_buf(priv, SPI_WRITE,
					   regs->mii_rx_clk[port], packed_buf,
					   SJA1105_SIZE_CGU_CMD);
	return sja1105_xfer_buf(priv, SPI_WRITE, regs->mii_rx_clk[port],
				packed_buf, SJA1105_SIZE_CGU_CMD);
}

static int
@@ -217,8 +214,7 @@ sja1105_cgu_mii_ext_tx_clk_config(struct sja1105_private *priv, int port)
	mii_ext_tx_clk.pd        = 0; /* Power Down off => enabled */
	sja1105_cgu_mii_control_packing(packed_buf, &mii_ext_tx_clk, PACK);

	return sja1105_spi_send_packed_buf(priv, SPI_WRITE,
					   regs->mii_ext_tx_clk[port],
	return sja1105_xfer_buf(priv, SPI_WRITE, regs->mii_ext_tx_clk[port],
				packed_buf, SJA1105_SIZE_CGU_CMD);
}

@@ -242,8 +238,7 @@ sja1105_cgu_mii_ext_rx_clk_config(struct sja1105_private *priv, int port)
	mii_ext_rx_clk.pd        = 0; /* Power Down off => enabled */
	sja1105_cgu_mii_control_packing(packed_buf, &mii_ext_rx_clk, PACK);

	return sja1105_spi_send_packed_buf(priv, SPI_WRITE,
					   regs->mii_ext_rx_clk[port],
	return sja1105_xfer_buf(priv, SPI_WRITE, regs->mii_ext_rx_clk[port],
				packed_buf, SJA1105_SIZE_CGU_CMD);
}

@@ -337,8 +332,7 @@ static int sja1105_cgu_rgmii_tx_clk_config(struct sja1105_private *priv,
	txc.pd = 0;
	sja1105_cgu_mii_control_packing(packed_buf, &txc, PACK);

	return sja1105_spi_send_packed_buf(priv, SPI_WRITE,
					   regs->rgmii_tx_clk[port],
	return sja1105_xfer_buf(priv, SPI_WRITE, regs->rgmii_tx_clk[port],
				packed_buf, SJA1105_SIZE_CGU_CMD);
}

@@ -383,8 +377,7 @@ static int sja1105_rgmii_cfg_pad_tx_config(struct sja1105_private *priv,
	pad_mii_tx.clk_ipud  = 2; /* TX_CLK input stage (default) */
	sja1105_cfg_pad_mii_tx_packing(packed_buf, &pad_mii_tx, PACK);

	return sja1105_spi_send_packed_buf(priv, SPI_WRITE,
					   regs->pad_mii_tx[port],
	return sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_tx[port],
				packed_buf, SJA1105_SIZE_CGU_CMD);
}

@@ -405,7 +398,7 @@ sja1105_cfg_pad_mii_id_packing(void *buf, struct sja1105_cfg_pad_mii_id *cmd,
}

/* Valid range in degrees is an integer between 73.8 and 101.7 */
static inline u64 sja1105_rgmii_delay(u64 phase)
static u64 sja1105_rgmii_delay(u64 phase)
{
	/* UM11040.pdf: The delay in degree phase is 73.8 + delay_tune * 0.9.
	 * To avoid floating point operations we'll multiply by 10
@@ -442,8 +435,7 @@ int sja1105pqrs_setup_rgmii_delay(const void *ctx, int port)
	pad_mii_id.txc_pd = 1;
	sja1105_cfg_pad_mii_id_packing(packed_buf, &pad_mii_id, PACK);

	rc = sja1105_spi_send_packed_buf(priv, SPI_WRITE,
					 regs->pad_mii_id[port],
	rc = sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_id[port],
			      packed_buf, SJA1105_SIZE_CGU_CMD);
	if (rc < 0)
		return rc;
@@ -459,8 +451,7 @@ int sja1105pqrs_setup_rgmii_delay(const void *ctx, int port)
	}
	sja1105_cfg_pad_mii_id_packing(packed_buf, &pad_mii_id, PACK);

	return sja1105_spi_send_packed_buf(priv, SPI_WRITE,
					   regs->pad_mii_id[port],
	return sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_id[port],
				packed_buf, SJA1105_SIZE_CGU_CMD);
}

@@ -547,8 +538,7 @@ static int sja1105_cgu_rmii_ref_clk_config(struct sja1105_private *priv,
	ref_clk.pd        = 0;      /* Power Down off => enabled */
	sja1105_cgu_mii_control_packing(packed_buf, &ref_clk, PACK);

	return sja1105_spi_send_packed_buf(priv, SPI_WRITE,
					   regs->rmii_ref_clk[port],
	return sja1105_xfer_buf(priv, SPI_WRITE, regs->rmii_ref_clk[port],
				packed_buf, SJA1105_SIZE_CGU_CMD);
}

@@ -565,8 +555,7 @@ sja1105_cgu_rmii_ext_tx_clk_config(struct sja1105_private *priv, int port)
	ext_tx_clk.pd        = 0;   /* Power Down off => enabled */
	sja1105_cgu_mii_control_packing(packed_buf, &ext_tx_clk, PACK);

	return sja1105_spi_send_packed_buf(priv, SPI_WRITE,
					   regs->rmii_ext_tx_clk[port],
	return sja1105_xfer_buf(priv, SPI_WRITE, regs->rmii_ext_tx_clk[port],
				packed_buf, SJA1105_SIZE_CGU_CMD);
}

@@ -595,8 +584,8 @@ static int sja1105_cgu_rmii_pll_config(struct sja1105_private *priv)
	pll.pd        = 0x1;

	sja1105_cgu_pll_control_packing(packed_buf, &pll, PACK);
	rc = sja1105_spi_send_packed_buf(priv, SPI_WRITE, regs->rmii_pll1,
					 packed_buf, SJA1105_SIZE_CGU_CMD);
	rc = sja1105_xfer_buf(priv, SPI_WRITE, regs->rmii_pll1, packed_buf,
			      SJA1105_SIZE_CGU_CMD);
	if (rc < 0) {
		dev_err(dev, "failed to configure PLL1 for 50MHz\n");
		return rc;
@@ -606,8 +595,8 @@ static int sja1105_cgu_rmii_pll_config(struct sja1105_private *priv)
	pll.pd = 0x0;

	sja1105_cgu_pll_control_packing(packed_buf, &pll, PACK);
	rc = sja1105_spi_send_packed_buf(priv, SPI_WRITE, regs->rmii_pll1,
					 packed_buf, SJA1105_SIZE_CGU_CMD);
	rc = sja1105_xfer_buf(priv, SPI_WRITE, regs->rmii_pll1, packed_buf,
			      SJA1105_SIZE_CGU_CMD);
	if (rc < 0) {
		dev_err(dev, "failed to enable PLL1\n");
		return rc;
+6 −6
Original line number Diff line number Diff line
@@ -686,8 +686,8 @@ int sja1105_dynamic_config_read(struct sja1105_private *priv,
		ops->entry_packing(packed_buf, entry, PACK);

	/* Send SPI write operation: read config table entry */
	rc = sja1105_spi_send_packed_buf(priv, SPI_WRITE, ops->addr,
					 packed_buf, ops->packed_size);
	rc = sja1105_xfer_buf(priv, SPI_WRITE, ops->addr, packed_buf,
			      ops->packed_size);
	if (rc < 0)
		return rc;

@@ -698,8 +698,8 @@ int sja1105_dynamic_config_read(struct sja1105_private *priv,
		memset(packed_buf, 0, ops->packed_size);

		/* Retrieve the read operation's result */
		rc = sja1105_spi_send_packed_buf(priv, SPI_READ, ops->addr,
						 packed_buf, ops->packed_size);
		rc = sja1105_xfer_buf(priv, SPI_READ, ops->addr, packed_buf,
				      ops->packed_size);
		if (rc < 0)
			return rc;

@@ -771,8 +771,8 @@ int sja1105_dynamic_config_write(struct sja1105_private *priv,
		ops->entry_packing(packed_buf, entry, PACK);

	/* Send SPI write operation: read config table entry */
	rc = sja1105_spi_send_packed_buf(priv, SPI_WRITE, ops->addr,
					 packed_buf, ops->packed_size);
	rc = sja1105_xfer_buf(priv, SPI_WRITE, ops->addr, packed_buf,
			      ops->packed_size);
	if (rc < 0)
		return rc;

+8 −8
Original line number Diff line number Diff line
@@ -167,8 +167,8 @@ static int sja1105_port_status_get_mac(struct sja1105_private *priv,
	int rc;

	/* MAC area */
	rc = sja1105_spi_send_packed_buf(priv, SPI_READ, regs->mac[port],
					 packed_buf, SJA1105_SIZE_MAC_AREA);
	rc = sja1105_xfer_buf(priv, SPI_READ, regs->mac[port], packed_buf,
			      SJA1105_SIZE_MAC_AREA);
	if (rc < 0)
		return rc;

@@ -185,8 +185,8 @@ static int sja1105_port_status_get_hl1(struct sja1105_private *priv,
	u8 packed_buf[SJA1105_SIZE_HL1_AREA] = {0};
	int rc;

	rc = sja1105_spi_send_packed_buf(priv, SPI_READ, regs->mac_hl1[port],
					 packed_buf, SJA1105_SIZE_HL1_AREA);
	rc = sja1105_xfer_buf(priv, SPI_READ, regs->mac_hl1[port], packed_buf,
			      SJA1105_SIZE_HL1_AREA);
	if (rc < 0)
		return rc;

@@ -203,8 +203,8 @@ static int sja1105_port_status_get_hl2(struct sja1105_private *priv,
	u8 packed_buf[SJA1105_SIZE_QLEVEL_AREA] = {0};
	int rc;

	rc = sja1105_spi_send_packed_buf(priv, SPI_READ, regs->mac_hl2[port],
					 packed_buf, SJA1105_SIZE_HL2_AREA);
	rc = sja1105_xfer_buf(priv, SPI_READ, regs->mac_hl2[port], packed_buf,
			      SJA1105_SIZE_HL2_AREA);
	if (rc < 0)
		return rc;

@@ -215,8 +215,8 @@ static int sja1105_port_status_get_hl2(struct sja1105_private *priv,
	    priv->info->device_id == SJA1105T_DEVICE_ID)
		return 0;

	rc = sja1105_spi_send_packed_buf(priv, SPI_READ, regs->qlevel[port],
					 packed_buf, SJA1105_SIZE_QLEVEL_AREA);
	rc = sja1105_xfer_buf(priv, SPI_READ, regs->qlevel[port], packed_buf,
			      SJA1105_SIZE_QLEVEL_AREA);
	if (rc < 0)
		return rc;

+8 −10
Original line number Diff line number Diff line
@@ -458,8 +458,7 @@ static int sja1105_init_general_params(struct sja1105_private *priv)

#define SJA1105_RATE_MBPS(speed) (((speed) * 64000) / 1000)

static inline void
sja1105_setup_policer(struct sja1105_l2_policing_entry *policing,
static void sja1105_setup_policer(struct sja1105_l2_policing_entry *policing,
				  int index)
{
	policing[index].sharindx = index;
@@ -951,7 +950,7 @@ sja1105_static_fdb_change(struct sja1105_private *priv, int port,
 * For the placement of a newly learnt FDB entry, the switch selects the bin
 * based on a hash function, and the way within that bin incrementally.
 */
static inline int sja1105et_fdb_index(int bin, int way)
static int sja1105et_fdb_index(int bin, int way)
{
	return bin * SJA1105ET_FDB_BIN_SIZE + way;
}
@@ -2110,23 +2109,22 @@ static int sja1105_check_device_id(struct sja1105_private *priv)
	const struct sja1105_regs *regs = priv->info->regs;
	u8 prod_id[SJA1105_SIZE_DEVICE_ID] = {0};
	struct device *dev = &priv->spidev->dev;
	u64 device_id;
	u32 device_id;
	u64 part_no;
	int rc;

	rc = sja1105_spi_send_int(priv, SPI_READ, regs->device_id,
				  &device_id, SJA1105_SIZE_DEVICE_ID);
	rc = sja1105_xfer_u32(priv, SPI_READ, regs->device_id, &device_id);
	if (rc < 0)
		return rc;

	if (device_id != priv->info->device_id) {
		dev_err(dev, "Expected device ID 0x%llx but read 0x%llx\n",
		dev_err(dev, "Expected device ID 0x%llx but read 0x%x\n",
			priv->info->device_id, device_id);
		return -ENODEV;
	}

	rc = sja1105_spi_send_packed_buf(priv, SPI_READ, regs->prod_id,
					 prod_id, SJA1105_SIZE_DEVICE_ID);
	rc = sja1105_xfer_buf(priv, SPI_READ, regs->prod_id, prod_id,
			      SJA1105_SIZE_DEVICE_ID);
	if (rc < 0)
		return rc;

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