Commit b73fe58c authored by Ben Widawsky's avatar Ben Widawsky Committed by Keith Packard
Browse files

drm: Add Panel Self Refresh DP addresses 



Add the addresses and definitions I care about for Panel Self Refresh, as
documented in the eDP spec.

I'm sending these out before some other patches because this should be a fairly
simple one to get upstream and not require too much fuss (where the others may
have some fuss).

This file is a mess with white spacing. I tried to stay consistent with the
surrounding code.

v2: had some silly mistakes in v1 which Keith caught

Cc: Dave Airlie <airlied@redhat.com>
Cc: Keith Packard <keithp@keithp.com>
Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
Signed-off-by: default avatarKeith Packard <keithp@keithp.com>
parent 5c042287

include/drm/drm_dp_helper.h

+36 −0
Original line number Diff line number Diff line
@@ -74,6 +74,20 @@ 


#define DP_TRAINING_AUX_RD_INTERVAL         0x00e



#define DP_PSR_SUPPORT                      0x070

# define DP_PSR_IS_SUPPORTED                1

#define DP_PSR_CAPS                         0x071

# define DP_PSR_NO_TRAIN_ON_EXIT            1

# define DP_PSR_SETUP_TIME_330              (0 << 1)

# define DP_PSR_SETUP_TIME_275              (1 << 1)

# define DP_PSR_SETUP_TIME_220              (2 << 1)

# define DP_PSR_SETUP_TIME_165              (3 << 1)

# define DP_PSR_SETUP_TIME_110              (4 << 1)

# define DP_PSR_SETUP_TIME_55               (5 << 1)

# define DP_PSR_SETUP_TIME_0                (6 << 1)

# define DP_PSR_SETUP_TIME_MASK             (7 << 1)

# define DP_PSR_SETUP_TIME_SHIFT            1



/* link configuration */

#define	DP_LINK_BW_SET		            0x100

# define DP_LINK_BW_1_62		    0x06
@@ -133,6 +147,12 @@ 
#define DP_MAIN_LINK_CHANNEL_CODING_SET	    0x108

# define DP_SET_ANSI_8B10B		    (1 << 0)



#define DP_PSR_EN_CFG			    0x170

# define DP_PSR_ENABLE			    (1 << 0)

# define DP_PSR_MAIN_LINK_ACTIVE	    (1 << 1)

# define DP_PSR_CRC_VERIFICATION	    (1 << 2)

# define DP_PSR_FRAME_CAPTURE		    (1 << 3)



#define DP_LANE0_1_STATUS		    0x202

#define DP_LANE2_3_STATUS		    0x203

# define DP_LANE_CR_DONE		    (1 << 0)
@@ -169,6 +189,22 @@ 
# define DP_SET_POWER_D0                    0x1

# define DP_SET_POWER_D3                    0x2



#define DP_PSR_ERROR_STATUS                 0x2006

# define DP_PSR_LINK_CRC_ERROR              (1 << 0)

# define DP_PSR_RFB_STORAGE_ERROR           (1 << 1)



#define DP_PSR_ESI                          0x2007

# define DP_PSR_CAPS_CHANGE                 (1 << 0)



#define DP_PSR_STATUS                       0x2008

# define DP_PSR_SINK_INACTIVE               0

# define DP_PSR_SINK_ACTIVE_SRC_SYNCED      1

# define DP_PSR_SINK_ACTIVE_RFB             2

# define DP_PSR_SINK_ACTIVE_SINK_SYNCED     3

# define DP_PSR_SINK_ACTIVE_RESYNC          4

# define DP_PSR_SINK_INTERNAL_ERROR         7

# define DP_PSR_SINK_STATE_MASK             0x07



#define MODE_I2C_START	1

#define MODE_I2C_WRITE	2

#define MODE_I2C_READ	4

CRA Git | Maintained and supported by SUSTech CRA and CCSE