Commit b7397bad authored by Bas Nieuwenhuizen's avatar Bas Nieuwenhuizen Committed by Alex Deucher
Browse files

drm/fourcc: Fix modifier field mask for AMD modifiers. 



The DCC_MAX_COMPRESSED_BLOCK has to contain one of
AMD_FMT_MOD_DCC_BLOCK_* and with 3 values this doesn't
fit in 1 bit.

Fix this cleanly while it is only in drm-next.

Fixes: 8ba16d59 ("drm/fourcc: Add AMD DRM modifiers.")
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarBas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 52f6f16d

include/uapi/drm/drm_fourcc.h

+7 −7
Original line number Diff line number Diff line
@@ -1168,7 +1168,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) 
#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17

#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1

#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18

#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x1

#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3



/*

 * DCC supports embedding some clear colors directly in the DCC surface.
@@ -1179,7 +1179,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) 
 * If this bit is set that means the fastclear eliminate is not needed for these

 * embeddable colors.

 */

#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 19

#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20

#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1



/*
@@ -1192,15 +1192,15 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) 
 * RB = only for TILE_VER_GFX9 & DCC

 * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN)

 */

#define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 20

#define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21

#define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7

#define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 23

#define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24

#define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7

#define AMD_FMT_MOD_PACKERS_SHIFT 26 /* aliases with BANK_XOR_BITS */

#define AMD_FMT_MOD_PACKERS_SHIFT 27 /* aliases with BANK_XOR_BITS */

#define AMD_FMT_MOD_PACKERS_MASK 0x7

#define AMD_FMT_MOD_RB_SHIFT 29

#define AMD_FMT_MOD_RB_SHIFT 30

#define AMD_FMT_MOD_RB_MASK 0x7

#define AMD_FMT_MOD_PIPE_SHIFT 32

#define AMD_FMT_MOD_PIPE_SHIFT 33

#define AMD_FMT_MOD_PIPE_MASK 0x7



#define AMD_FMT_MOD_SET(field, value) \

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