Commit b71b477d authored by Aditya Swarup's avatar Aditya Swarup Committed by Lucas De Marchi
Browse files

drm/i915/dg1: Add and setup DPLLs for DG1 



Add entries for dg1 plls and setup dg1_pll_mgr to reuse ICL callbacks.
Initial setup for shared dplls DPLL0/1 for DDIA/DDIB and DPLL2/3 for
DDI-TC1/DDI-TC2. Configure dpll cfgcrx registers to drive the plls on
DG1.

v2 (Lucas): Reword commit message and add missing update_ref_clks hook
   (requested by Matt Roper)

Signed-off-by: default avatarAditya Swarup <aditya.swarup@intel.com>
Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201014191937.1266226-5-lucas.demarchi@intel.com
parent 049c651b

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

+38 −4
Original line number Diff line number Diff line
@@ -3546,7 +3546,17 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state, 


	icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);



	if (IS_ROCKETLAKE(dev_priv)) {

	if (IS_DG1(dev_priv)) {

		if (port == PORT_D || port == PORT_E) {

			dpll_mask =

				BIT(DPLL_ID_DG1_DPLL2) |

				BIT(DPLL_ID_DG1_DPLL3);

		} else {

			dpll_mask =

				BIT(DPLL_ID_DG1_DPLL0) |

				BIT(DPLL_ID_DG1_DPLL1);

		}

	} else if (IS_ROCKETLAKE(dev_priv)) {

		dpll_mask =

			BIT(DPLL_ID_EHL_DPLL4) |

			BIT(DPLL_ID_ICL_DPLL1) |
@@ -3842,7 +3852,10 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv, 
	if (!(val & PLL_ENABLE))

		goto out;



	if (IS_ROCKETLAKE(dev_priv)) {

	if (IS_DG1(dev_priv)) {

		hw_state->cfgcr0 = intel_de_read(dev_priv, DG1_DPLL_CFGCR0(id));

		hw_state->cfgcr1 = intel_de_read(dev_priv, DG1_DPLL_CFGCR1(id));

	} else if (IS_ROCKETLAKE(dev_priv)) {

		hw_state->cfgcr0 = intel_de_read(dev_priv,

						 RKL_DPLL_CFGCR0(id));

		hw_state->cfgcr1 = intel_de_read(dev_priv,
@@ -3895,7 +3908,10 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv, 
	const enum intel_dpll_id id = pll->info->id;

	i915_reg_t cfgcr0_reg, cfgcr1_reg;



	if (IS_ROCKETLAKE(dev_priv)) {

	if (IS_DG1(dev_priv)) {

		cfgcr0_reg = DG1_DPLL_CFGCR0(id);

		cfgcr1_reg = DG1_DPLL_CFGCR1(id);

	} else if (IS_ROCKETLAKE(dev_priv)) {

		cfgcr0_reg = RKL_DPLL_CFGCR0(id);

		cfgcr1_reg = RKL_DPLL_CFGCR1(id);

	} else if (INTEL_GEN(dev_priv) >= 12) {
@@ -4339,6 +4355,22 @@ static const struct intel_dpll_mgr rkl_pll_mgr = { 
	.dump_hw_state = icl_dump_hw_state,

};



static const struct dpll_info dg1_plls[] = {

	{ "DPLL 0", &combo_pll_funcs, DPLL_ID_DG1_DPLL0, 0 },

	{ "DPLL 1", &combo_pll_funcs, DPLL_ID_DG1_DPLL1, 0 },

	{ "DPLL 2", &combo_pll_funcs, DPLL_ID_DG1_DPLL2, 0 },

	{ "DPLL 3", &combo_pll_funcs, DPLL_ID_DG1_DPLL3, 0 },

	{ },

};



static const struct intel_dpll_mgr dg1_pll_mgr = {

	.dpll_info = dg1_plls,

	.get_dplls = icl_get_dplls,

	.put_dplls = icl_put_dplls,

	.update_ref_clks = icl_update_dpll_ref_clks,

	.dump_hw_state = icl_dump_hw_state,

};



/**

 * intel_shared_dpll_init - Initialize shared DPLLs

 * @dev: drm device
@@ -4352,7 +4384,9 @@ void intel_shared_dpll_init(struct drm_device *dev) 
	const struct dpll_info *dpll_info;

	int i;



	if (IS_ROCKETLAKE(dev_priv))

	if (IS_DG1(dev_priv))

		dpll_mgr = &dg1_pll_mgr;

	else if (IS_ROCKETLAKE(dev_priv))

		dpll_mgr = &rkl_pll_mgr;

	else if (INTEL_GEN(dev_priv) >= 12)

		dpll_mgr = &tgl_pll_mgr;

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