Commit b6ffa050 authored by Paul Walmsley's avatar Paul Walmsley
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ARM: OMAP2xxx: APLL/CM: convert to use omap2_cm_wait_module_ready() 



Convert the OMAP2xxx APLL code to use omap2_cm_wait_module_ready(),
and move the low-level CM register manipulation functions to
mach-omap2/cm2xxx.c.  The objectives here are to remove the dependency
on the deprecated omap2_cm_wait_idlest() function in
mach-omap2/prcm.c, so that code can be removed later; and move
low-level register accesses to the CM IP block to the CM code, which
will soon be moved into drivers/.

Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
Tested-by: default avatarVaibhav Hiremath <hvaibhav@ti.com>
parent 187e3e06

arch/arm/mach-omap2/clkt2xxx_apll.c

+14 −42
Original line number Original line Diff line number Diff line
@@ -37,44 +37,16 @@ 
#define APLLS_CLKIN_13MHZ		2

#define APLLS_CLKIN_13MHZ		2

#define APLLS_CLKIN_12MHZ		3

#define APLLS_CLKIN_12MHZ		3





void __iomem *cm_idlest_pll;



/* Private functions */

/* Private functions */





/* Enable an APLL if off */

static int _apll96_enable(struct clk *clk)

static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)

{

	u32 cval, apll_mask;



	apll_mask = EN_APLL_LOCKED << clk->enable_bit;



	cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);



	if ((cval & apll_mask) == apll_mask)

		return 0;   /* apll already enabled */



	cval &= ~apll_mask;

	cval |= apll_mask;

	omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);



	omap2_cm_wait_idlest(cm_idlest_pll, status_mask,

			     OMAP24XX_CM_IDLEST_VAL, __clk_get_name(clk));



	/*

	 * REVISIT: Should we return an error code if omap2_wait_clock_ready()

	 * fails?

	 */

	return 0;

}



static int omap2_clk_apll96_enable(struct clk *clk)

{

{

	return omap2_clk_apll_enable(clk, OMAP24XX_ST_96M_APLL_MASK);

	return omap2xxx_cm_apll96_enable();

}

}





static int omap2_clk_apll54_enable(struct clk *clk)

static int _apll54_enable(struct clk *clk)

{

{

	return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL_MASK);

	return omap2xxx_cm_apll54_enable();

}

}





static void _apll96_allow_idle(struct clk *clk)

static void _apll96_allow_idle(struct clk *clk)
@@ -97,28 +69,28 @@ static void _apll54_deny_idle(struct clk *clk) 
	omap2xxx_cm_set_apll54_disable_autoidle();

	omap2xxx_cm_set_apll54_disable_autoidle();

}

}





/* Stop APLL */

static void _apll96_disable(struct clk *clk)

static void omap2_clk_apll_disable(struct clk *clk)

{

{

	u32 cval;

	omap2xxx_cm_apll96_disable();

}





	cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);

static void _apll54_disable(struct clk *clk)

	cval &= ~(EN_APLL_LOCKED << clk->enable_bit);

{

	omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);

	omap2xxx_cm_apll54_disable();

}

}





/* Public data */

/* Public data */





const struct clkops clkops_apll96 = {

const struct clkops clkops_apll96 = {

	.enable		= omap2_clk_apll96_enable,

	.enable		= _apll96_enable,

	.disable	= omap2_clk_apll_disable,

	.disable	= _apll96_disable,

	.allow_idle	= _apll96_allow_idle,

	.allow_idle	= _apll96_allow_idle,

	.deny_idle	= _apll96_deny_idle,

	.deny_idle	= _apll96_deny_idle,

};

};





const struct clkops clkops_apll54 = {

const struct clkops clkops_apll54 = {

	.enable		= omap2_clk_apll54_enable,

	.enable		= _apll54_enable,

	.disable	= omap2_clk_apll_disable,

	.disable	= _apll54_disable,

	.allow_idle	= _apll54_allow_idle,

	.allow_idle	= _apll54_allow_idle,

	.deny_idle	= _apll54_deny_idle,

	.deny_idle	= _apll54_deny_idle,

};

};

arch/arm/mach-omap2/clock2420_data.c

+0 −1
Original line number Original line Diff line number Diff line
@@ -1928,7 +1928,6 @@ int __init omap2420_clk_init(void) 
	struct omap_clk *c;

	struct omap_clk *c;





	prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;

	prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;

	cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST);

	cpu_mask = RATE_IN_242X;

	cpu_mask = RATE_IN_242X;

	rate_table = omap2420_rate_table;

	rate_table = omap2420_rate_table;

arch/arm/mach-omap2/clock2430_data.c

+0 −1
Original line number Original line Diff line number Diff line
@@ -2027,7 +2027,6 @@ int __init omap2430_clk_init(void) 
	struct omap_clk *c;

	struct omap_clk *c;





	prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;

	prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;

	cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST);

	cpu_mask = RATE_IN_243X;

	cpu_mask = RATE_IN_243X;

	rate_table = omap2430_rate_table;

	rate_table = omap2430_rate_table;

arch/arm/mach-omap2/clock2xxx.h

+1 −1
Original line number Original line Diff line number Diff line
@@ -35,7 +35,7 @@ int omap2430_clk_init(void); 
#define omap2430_clk_init()	do { } while(0)

#define omap2430_clk_init()	do { } while(0)

#endif

#endif





extern void __iomem *prcm_clksrc_ctrl, *cm_idlest_pll;

extern void __iomem *prcm_clksrc_ctrl;





extern const struct clkops clkops_omap2430_i2chs_wait;

extern const struct clkops clkops_omap2430_i2chs_wait;

extern const struct clkops clkops_oscck;

extern const struct clkops clkops_oscck;

arch/arm/mach-omap2/cm-regbits-24xx.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -333,7 +333,9 @@ 
#define OMAP24XX_EN_DPLL_MASK				(0x3 << 0)

#define OMAP24XX_EN_DPLL_MASK				(0x3 << 0)





/* CM_IDLEST_CKGEN */

/* CM_IDLEST_CKGEN */

#define OMAP24XX_ST_54M_APLL_SHIFT			9

#define OMAP24XX_ST_54M_APLL_MASK			(1 << 9)

#define OMAP24XX_ST_54M_APLL_MASK			(1 << 9)

#define OMAP24XX_ST_96M_APLL_SHIFT			8

#define OMAP24XX_ST_96M_APLL_MASK			(1 << 8)

#define OMAP24XX_ST_96M_APLL_MASK			(1 << 8)

#define OMAP24XX_ST_54M_CLK_MASK			(1 << 6)

#define OMAP24XX_ST_54M_CLK_MASK			(1 << 6)

#define OMAP24XX_ST_12M_CLK_MASK			(1 << 5)

#define OMAP24XX_ST_12M_CLK_MASK			(1 << 5)

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