Commit b6a03d04 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'omap-for-v3.9/gpmc-signed' of... 

Merge tag 'omap-for-v3.9/gpmc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers

From Tony Lindgren:
OMAP GPMC (General Purpose Memory Controller) changes to add
device tree bindings.

* tag 'omap-for-v3.9/gpmc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap

:
  ARM: OMAP2+: gpmc: Add device tree documentation for elm handle
  ARM: OMAP2+: gpmc: add DT bindings for OneNAND
  ARM: OMAP2+: gpmc-onenand: drop __init annotation
  mtd: omap-onenand: pass device_node in platform data
  ARM: OMAP2+: Prevent potential crash if GPMC probe fails
  ARM: OMAP2+: gpmc: Remove unneeded of_node_put()
  ARM: OMAP: gpmc: add DT bindings for GPMC timings and NAND
  ARM: OMAP: gpmc: enable hwecc for AM33xx SoCs
  ARM: OMAP: gpmc-nand: drop __init annotation
  mtd: omap-nand: pass device_node in platform data
  ARM: OMAP: gpmc: don't create devices from initcall on DT

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 3e93093e 97c794a1

Documentation/devicetree/bindings/bus/ti-gpmc.txt

0 → 100644
+84 −0
Original line number Diff line number Diff line 
Device tree bindings for OMAP general purpose memory controllers (GPMC)



The actual devices are instantiated from the child nodes of a GPMC node.



Required properties:



 - compatible:		Should be set to one of the following:



			ti,omap2420-gpmc (omap2420)

			ti,omap2430-gpmc (omap2430)

			ti,omap3430-gpmc (omap3430 & omap3630)

			ti,omap4430-gpmc (omap4430 & omap4460 & omap543x)

			ti,am3352-gpmc   (am335x devices)



 - reg:			A resource specifier for the register space

			(see the example below)

 - ti,hwmods:		Should be set to "ti,gpmc" until the DT transition is

			completed.

 - #address-cells:	Must be set to 2 to allow memory address translation

 - #size-cells:		Must be set to 1 to allow CS address passing

 - gpmc,num-cs:		The maximum number of chip-select lines that controller

			can support.

 - gpmc,num-waitpins:	The maximum number of wait pins that controller can

			support.

 - ranges:		Must be set up to reflect the memory layout with four

			integer values for each chip-select line in use:



			   <cs-number> 0 <physical address of mapping> <size>



			Currently, calculated values derived from the contents

			of the per-CS register GPMC_CONFIG7 (as set up by the

			bootloader) are used for the physical address decoding.

			As this will change in the future, filling correct

			values here is a requirement.



Timing properties for child nodes. All are optional and default to 0.



 - gpmc,sync-clk:	Minimum clock period for synchronous mode, in picoseconds



 Chip-select signal timings corresponding to GPMC_CONFIG2:

 - gpmc,cs-on:		Assertion time

 - gpmc,cs-rd-off:	Read deassertion time

 - gpmc,cs-wr-off:	Write deassertion time



 ADV signal timings corresponding to GPMC_CONFIG3:

 - gpmc,adv-on:		Assertion time

 - gpmc,adv-rd-off:	Read deassertion time

 - gpmc,adv-wr-off:	Write deassertion time



 WE signals timings corresponding to GPMC_CONFIG4:

 - gpmc,we-on:		Assertion time

 - gpmc,we-off:		Deassertion time



 OE signals timings corresponding to GPMC_CONFIG4:

 - gpmc,oe-on:		Assertion time

 - gpmc,oe-off:		Deassertion time



 Access time and cycle time timings corresponding to GPMC_CONFIG5:

 - gpmc,page-burst-access: Multiple access word delay

 - gpmc,access:		Start-cycle to first data valid delay

 - gpmc,rd-cycle:	Total read cycle time

 - gpmc,wr-cycle:	Total write cycle time



The following are only applicable to OMAP3+ and AM335x:

 - gpmc,wr-access

 - gpmc,wr-data-mux-bus





Example for an AM33xx board:



	gpmc: gpmc@50000000 {

		compatible = "ti,am3352-gpmc";

		ti,hwmods = "gpmc";

		reg = <0x50000000 0x2000>;

		interrupts = <100>;



		gpmc,num-cs = <8>;

		gpmc,num-waitpins = <2>;

		#address-cells = <2>;

		#size-cells = <1>;

		ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */



		/* child nodes go here */

	};

Documentation/devicetree/bindings/mtd/gpmc-nand.txt

0 → 100644
+80 −0
Original line number Diff line number Diff line 
Device tree bindings for GPMC connected NANDs



GPMC connected NAND (found on OMAP boards) are represented as child nodes of

the GPMC controller with a name of "nand".



All timing relevant properties as well as generic gpmc child properties are

explained in a separate documents - please refer to

Documentation/devicetree/bindings/bus/ti-gpmc.txt



For NAND specific properties such as ECC modes or bus width, please refer to

Documentation/devicetree/bindings/mtd/nand.txt





Required properties:



 - reg:		The CS line the peripheral is connected to



Optional properties:



 - nand-bus-width: 		Set this numeric value to 16 if the hardware

				is wired that way. If not specified, a bus

				width of 8 is assumed.



 - ti,nand-ecc-opt:		A string setting the ECC layout to use. One of:



		"sw"		Software method (default)

		"hw"		Hardware method

		"hw-romcode"	gpmc hamming mode method & romcode layout

		"bch4"		4-bit BCH ecc code

		"bch8"		8-bit BCH ecc code



 - elm_id:	Specifies elm device node. This is required to support BCH

 		error correction using ELM module.



For inline partiton table parsing (optional):



 - #address-cells: should be set to 1

 - #size-cells: should be set to 1



Example for an AM33xx board:



	gpmc: gpmc@50000000 {

		compatible = "ti,am3352-gpmc";

		ti,hwmods = "gpmc";

		reg = <0x50000000 0x1000000>;

		interrupts = <100>;

		gpmc,num-cs = <8>;

		gpmc,num-waitpins = <2>;

		#address-cells = <2>;

		#size-cells = <1>;

		ranges = <0 0 0x08000000 0x2000>;	/* CS0: NAND */

		elm_id = <&elm>;



		nand@0,0 {

			reg = <0 0 0>; /* CS0, offset 0 */

			nand-bus-width = <16>;

			ti,nand-ecc-opt = "bch8";



			gpmc,sync-clk = <0>;

			gpmc,cs-on = <0>;

			gpmc,cs-rd-off = <44>;

			gpmc,cs-wr-off = <44>;

			gpmc,adv-on = <6>;

			gpmc,adv-rd-off = <34>;

			gpmc,adv-wr-off = <44>;

			gpmc,we-off = <40>;

			gpmc,oe-off = <54>;

			gpmc,access = <64>;

			gpmc,rd-cycle = <82>;

			gpmc,wr-cycle = <82>;

			gpmc,wr-access = <40>;

			gpmc,wr-data-mux-bus = <0>;



			#address-cells = <1>;

			#size-cells = <1>;



			/* partitions go here */

		};

	};

Documentation/devicetree/bindings/mtd/gpmc-onenand.txt

0 → 100644
+43 −0
Original line number Diff line number Diff line 
Device tree bindings for GPMC connected OneNANDs



GPMC connected OneNAND (found on OMAP boards) are represented as child nodes of

the GPMC controller with a name of "onenand".



All timing relevant properties as well as generic gpmc child properties are

explained in a separate documents - please refer to

Documentation/devicetree/bindings/bus/ti-gpmc.txt



Required properties:



 - reg:			The CS line the peripheral is connected to



Optional properties:



 - dma-channel:		DMA Channel index



For inline partiton table parsing (optional):



 - #address-cells: should be set to 1

 - #size-cells: should be set to 1



Example for an OMAP3430 board:



	gpmc: gpmc@6e000000 {

		compatible = "ti,omap3430-gpmc";

		ti,hwmods = "gpmc";

		reg = <0x6e000000 0x1000000>;

		interrupts = <20>;

		gpmc,num-cs = <8>;

		gpmc,num-waitpins = <4>;

		#address-cells = <2>;

		#size-cells = <1>;



		onenand@0 {

			reg = <0 0 0>; /* CS0, offset 0 */



			#address-cells = <1>;

			#size-cells = <1>;



			/* partitions go here */

		};

	};

arch/arm/mach-omap2/gpmc-nand.c

+8 −7
Original line number Diff line number Diff line
@@ -89,20 +89,21 @@ static int omap2_nand_gpmc_retime( 
	return 0;

}



static bool __init gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)

static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)

{

	/* support only OMAP3 class */

	if (!cpu_is_omap34xx()) {

	if (!cpu_is_omap34xx() && !soc_is_am33xx()) {

		pr_err("BCH ecc is not supported on this CPU\n");

		return 0;

	}



	/*

	 * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1.

	 * Other chips may be added if confirmed to work.

	 * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1

	 * and AM33xx derivates. Other chips may be added if confirmed to work.

	 */

	if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) &&

	    (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) {

	    (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0)) &&

	    (!soc_is_am33xx())) {

		pr_err("BCH 4-bit mode is not supported on this CPU\n");

		return 0;

	}
@@ -110,7 +111,7 @@ static bool __init gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) 
	return 1;

}



int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,

int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,

		   struct gpmc_timings *gpmc_t)

{

	int err	= 0;

arch/arm/mach-omap2/gpmc-onenand.c

+1 −1
Original line number Diff line number Diff line
@@ -356,7 +356,7 @@ static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr) 
	return ret;

}



void __init gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)

void gpmc_onenand_init(struct omap_onenand_platform_data *_onenand_data)

{

	int err;

CRA Git | Maintained and supported by SUSTech CRA and CCSE