Commit b69f9e17 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'powerpc-4.20-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux 

Pull powerpc fixes from Michael Ellerman:
 "Some things that I missed due to travel, or that came in late.

  Two fixes also going to stable:

   - A revert of a buggy change to the 8xx TLB miss handlers.

   - Our flushing of SPE (Signal Processing Engine) registers on fork
     was broken.

  Other changes:

   - A change to the KVM decrementer emulation to use proper APIs.

   - Some cleanups to the way we do code patching in the 8xx code.

   - Expose the maximum possible memory for the system in
     /proc/powerpc/lparcfg.

   - Merge some updates from Scott: "a couple device tree updates, and a
     fix for a missing prototype warning"

  A few other minor fixes and a handful of fixes for our selftests.

  Thanks to: Aravinda Prasad, Breno Leitao, Camelia Groza, Christophe
  Leroy, Felipe Rechia, Joel Stanley, Naveen N. Rao, Paul Mackerras,
  Scott Wood, Tyrel Datwyler"

* tag 'powerpc-4.20-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: (21 commits)
  selftests/powerpc: Fix compilation issue due to asm label
  selftests/powerpc/cache_shape: Fix out-of-tree build
  selftests/powerpc/switch_endian: Fix out-of-tree build
  selftests/powerpc/pmu: Link ebb tests with -no-pie
  selftests/powerpc/signal: Fix out-of-tree build
  selftests/powerpc/ptrace: Fix out-of-tree build
  powerpc/xmon: Relax frame size for clang
  selftests: powerpc: Fix warning for security subdir
  selftests/powerpc: Relax L1d miss targets for rfi_flush test
  powerpc/process: Fix flush_all_to_thread for SPE
  powerpc/pseries: add missing cpumask.h include file
  selftests/powerpc: Fix ptrace tm failure
  KVM: PPC: Use exported tb_to_ns() function in decrementer emulation
  powerpc/pseries: Export maximum memory value
  powerpc/8xx: Use patch_site for perf counters setup
  powerpc/8xx: Use patch_site for memory setup patching
  powerpc/code-patching: Add a helper to get the address of a patch_site
  Revert "powerpc/8xx: Use L1 entry APG to handle _PAGE_ACCESSED for CONFIG_SWAP"
  powerpc/8xx: add missing header in 8xx_mmu.c
  powerpc/8xx: Add DT node for using the SEC engine of the MPC885
  ...
parents 63c6e188 1936f094

arch/powerpc/boot/dts/fsl/t2080rdb.dts

+2 −2
Original line number Original line Diff line number Diff line
@@ -77,12 +77,12 @@ 
		};

		};





		ethernet@f0000 {

		ethernet@f0000 {

			phy-handle = <&xg_cs4315_phy1>;

			phy-handle = <&xg_cs4315_phy2>;

			phy-connection-type = "xgmii";

			phy-connection-type = "xgmii";

		};

		};





		ethernet@f2000 {

		ethernet@f2000 {

			phy-handle = <&xg_cs4315_phy2>;

			phy-handle = <&xg_cs4315_phy1>;

			phy-connection-type = "xgmii";

			phy-connection-type = "xgmii";

		};

		};

arch/powerpc/boot/dts/mpc885ads.dts

+12 −1
Original line number Original line Diff line number Diff line
@@ -72,7 +72,7 @@ 
		#address-cells = <1>;

		#address-cells = <1>;

		#size-cells = <1>;

		#size-cells = <1>;

		device_type = "soc";

		device_type = "soc";

		ranges = <0x0 0xff000000 0x4000>;

		ranges = <0x0 0xff000000 0x28000>;

		bus-frequency = <0>;

		bus-frequency = <0>;





		// Temporary -- will go away once kernel uses ranges for get_immrbase().

		// Temporary -- will go away once kernel uses ranges for get_immrbase().
@@ -224,6 +224,17 @@ 
				#size-cells = <0>;

				#size-cells = <0>;

			};

			};

		};

		};



		crypto@20000 {

			compatible = "fsl,sec1.2", "fsl,sec1.0";

			reg = <0x20000 0x8000>;

			interrupts = <1 1>;

			interrupt-parent = <&PIC>;

			fsl,num-channels = <1>;

			fsl,channel-fifo-len = <24>;

			fsl,exec-units-mask = <0x4c>;

			fsl,descriptor-types-mask = <0x05000154>;

		};

	};

	};





	chosen {

	chosen {

arch/powerpc/include/asm/code-patching.h

+5 −0
Original line number Original line Diff line number Diff line
@@ -36,6 +36,11 @@ int raw_patch_instruction(unsigned int *addr, unsigned int instr); 
int patch_instruction_site(s32 *addr, unsigned int instr);

int patch_instruction_site(s32 *addr, unsigned int instr);

int patch_branch_site(s32 *site, unsigned long target, int flags);

int patch_branch_site(s32 *site, unsigned long target, int flags);





static inline unsigned long patch_site_addr(s32 *site)

{

	return (unsigned long)site + *site;

}



int instr_is_relative_branch(unsigned int instr);

int instr_is_relative_branch(unsigned int instr);

int instr_is_relative_link_branch(unsigned int instr);

int instr_is_relative_link_branch(unsigned int instr);

int instr_is_branch_to_addr(const unsigned int *instr, unsigned long addr);

int instr_is_branch_to_addr(const unsigned int *instr, unsigned long addr);

arch/powerpc/include/asm/mmu-8xx.h

+15 −28
Original line number Original line Diff line number Diff line
@@ -34,20 +34,12 @@ 
 * respectively NA for All or X for Supervisor and no access for User.

 * respectively NA for All or X for Supervisor and no access for User.

 * Then we use the APG to say whether accesses are according to Page rules or

 * Then we use the APG to say whether accesses are according to Page rules or

 * "all Supervisor" rules (Access to all)

 * "all Supervisor" rules (Access to all)

 * We also use the 2nd APG bit for _PAGE_ACCESSED when having SWAP:

 * Therefore, we define 2 APG groups. lsb is _PMD_USER

 * When that bit is not set access is done iaw "all user"

 * 0 => No user => 01 (all accesses performed according to page definition)

 * which means no access iaw page rules.

 * 1 => User => 00 (all accesses performed as supervisor iaw page definition)

 * Therefore, we define 4 APG groups. lsb is _PMD_USER, 2nd is _PAGE_ACCESSED

 * 0x => No access => 11 (all accesses performed as user iaw page definition)

 * 10 => No user => 01 (all accesses performed according to page definition)

 * 11 => User => 00 (all accesses performed as supervisor iaw page definition)

 * We define all 16 groups so that all other bits of APG can take any value

 * We define all 16 groups so that all other bits of APG can take any value

 */

 */

#ifdef CONFIG_SWAP

#define MI_APG_INIT	0xf4f4f4f4

#else

#define MI_APG_INIT	0x44444444

#define MI_APG_INIT	0x44444444

#endif





/* The effective page number register.  When read, contains the information

/* The effective page number register.  When read, contains the information

 * about the last instruction TLB miss.  When MI_RPN is written, bits in

 * about the last instruction TLB miss.  When MI_RPN is written, bits in
@@ -115,20 +107,12 @@ 
 * Supervisor and no access for user and NA for ALL.

 * Supervisor and no access for user and NA for ALL.

 * Then we use the APG to say whether accesses are according to Page rules or

 * Then we use the APG to say whether accesses are according to Page rules or

 * "all Supervisor" rules (Access to all)

 * "all Supervisor" rules (Access to all)

 * We also use the 2nd APG bit for _PAGE_ACCESSED when having SWAP:

 * Therefore, we define 2 APG groups. lsb is _PMD_USER

 * When that bit is not set access is done iaw "all user"

 * 0 => No user => 01 (all accesses performed according to page definition)

 * which means no access iaw page rules.

 * 1 => User => 00 (all accesses performed as supervisor iaw page definition)

 * Therefore, we define 4 APG groups. lsb is _PMD_USER, 2nd is _PAGE_ACCESSED

 * 0x => No access => 11 (all accesses performed as user iaw page definition)

 * 10 => No user => 01 (all accesses performed according to page definition)

 * 11 => User => 00 (all accesses performed as supervisor iaw page definition)

 * We define all 16 groups so that all other bits of APG can take any value

 * We define all 16 groups so that all other bits of APG can take any value

 */

 */

#ifdef CONFIG_SWAP

#define MD_APG_INIT	0xf4f4f4f4

#else

#define MD_APG_INIT	0x44444444

#define MD_APG_INIT	0x44444444

#endif





/* The effective page number register.  When read, contains the information

/* The effective page number register.  When read, contains the information

 * about the last instruction TLB miss.  When MD_RPN is written, bits in

 * about the last instruction TLB miss.  When MD_RPN is written, bits in
@@ -180,12 +164,6 @@ 
 */

 */

#define SPRN_M_TW	799

#define SPRN_M_TW	799





/* APGs */

#define M_APG0		0x00000000

#define M_APG1		0x00000020

#define M_APG2		0x00000040

#define M_APG3		0x00000060



#ifdef CONFIG_PPC_MM_SLICES

#ifdef CONFIG_PPC_MM_SLICES

#include <asm/nohash/32/slice.h>

#include <asm/nohash/32/slice.h>

#define SLICE_ARRAY_SIZE	(1 << (32 - SLICE_LOW_SHIFT - 1))

#define SLICE_ARRAY_SIZE	(1 << (32 - SLICE_LOW_SHIFT - 1))
@@ -251,6 +229,15 @@ static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize) 
	BUG();

	BUG();

}

}





/* patch sites */

extern s32 patch__itlbmiss_linmem_top;

extern s32 patch__dtlbmiss_linmem_top, patch__dtlbmiss_immr_jmp;

extern s32 patch__fixupdar_linmem_top;



extern s32 patch__itlbmiss_exit_1, patch__itlbmiss_exit_2;

extern s32 patch__dtlbmiss_exit_1, patch__dtlbmiss_exit_2, patch__dtlbmiss_exit_3;

extern s32 patch__itlbmiss_perf, patch__dtlbmiss_perf;



#endif /* !__ASSEMBLY__ */

#endif /* !__ASSEMBLY__ */





#if defined(CONFIG_PPC_4K_PAGES)

#if defined(CONFIG_PPC_4K_PAGES)

arch/powerpc/include/asm/rtas.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -5,6 +5,7 @@ 
#include <linux/spinlock.h>

#include <linux/spinlock.h>

#include <asm/page.h>

#include <asm/page.h>

#include <linux/time.h>

#include <linux/time.h>

#include <linux/cpumask.h>





/*

/*

 * Definitions for talking to the RTAS on CHRP machines.

 * Definitions for talking to the RTAS on CHRP machines.

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