Merge branch 'MSCC-PHY-RGMII-delays-and-VSC8502-support' (b69bbab5) · Commits · 戴 / test

drivers/net/phy/mscc/mscc.h

+12 −9

Original line number	Diff line number	Diff line
		@@ -12,15 +12,15 @@
		#include "mscc_macsec.h"
		#endif

		enum rgmii_rx_clock_delay {
		RGMII_RX_CLK_DELAY_0_2_NS = 0,
		RGMII_RX_CLK_DELAY_0_8_NS = 1,
		RGMII_RX_CLK_DELAY_1_1_NS = 2,
		RGMII_RX_CLK_DELAY_1_7_NS = 3,
		RGMII_RX_CLK_DELAY_2_0_NS = 4,
		RGMII_RX_CLK_DELAY_2_3_NS = 5,
		RGMII_RX_CLK_DELAY_2_6_NS = 6,
		RGMII_RX_CLK_DELAY_3_4_NS = 7
		enum rgmii_clock_delay {
		RGMII_CLK_DELAY_0_2_NS = 0,
		RGMII_CLK_DELAY_0_8_NS = 1,
		RGMII_CLK_DELAY_1_1_NS = 2,
		RGMII_CLK_DELAY_1_7_NS = 3,
		RGMII_CLK_DELAY_2_0_NS = 4,
		RGMII_CLK_DELAY_2_3_NS = 5,
		RGMII_CLK_DELAY_2_6_NS = 6,
		RGMII_CLK_DELAY_3_4_NS = 7
		};

		/* Microsemi VSC85xx PHY registers */
		@@ -178,6 +178,8 @@ enum rgmii_rx_clock_delay {
		#define MSCC_PHY_RGMII_CNTL 20
		#define RGMII_RX_CLK_DELAY_MASK 0x0070
		#define RGMII_RX_CLK_DELAY_POS 4
		#define RGMII_TX_CLK_DELAY_MASK 0x0007
		#define RGMII_TX_CLK_DELAY_POS 0

		#define MSCC_PHY_WOL_LOWER_MAC_ADDR 21
		#define MSCC_PHY_WOL_MID_MAC_ADDR 22
		@@ -274,6 +276,7 @@ enum rgmii_rx_clock_delay {
		/* Microsemi PHY ID's
		* Code assumes lowest nibble is 0
		*/
		#define PHY_ID_VSC8502 0x00070630
		#define PHY_ID_VSC8504 0x000704c0
		#define PHY_ID_VSC8514 0x00070670
		#define PHY_ID_VSC8530 0x00070560

drivers/net/phy/mscc/mscc_main.c

+40 −3

Original line number	Diff line number	Diff line
		@@ -491,6 +491,9 @@ static int vsc85xx_mac_if_set(struct phy_device *phydev,
		reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1);
		reg_val &= ~(MAC_IF_SELECTION_MASK);
		switch (interface) {
		case PHY_INTERFACE_MODE_RGMII_TXID:
		case PHY_INTERFACE_MODE_RGMII_RXID:
		case PHY_INTERFACE_MODE_RGMII_ID:
		case PHY_INTERFACE_MODE_RGMII:
		reg_val \|= (MAC_IF_SELECTION_RGMII << MAC_IF_SELECTION_POS);
		break;
		@@ -519,16 +522,26 @@ out_unlock:

		static int vsc85xx_default_config(struct phy_device *phydev)
		{
		u16 reg_val = 0;
		int rc;
		u16 reg_val;

		phydev->mdix_ctrl = ETH_TP_MDI_AUTO;

		if (!phy_interface_mode_is_rgmii(phydev->interface))
		return 0;

		mutex_lock(&phydev->lock);

		reg_val = RGMII_RX_CLK_DELAY_1_1_NS << RGMII_RX_CLK_DELAY_POS;
		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID \|\|
		phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
		reg_val \|= RGMII_CLK_DELAY_2_0_NS << RGMII_RX_CLK_DELAY_POS;
		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID \|\|
		phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
		reg_val \|= RGMII_CLK_DELAY_2_0_NS << RGMII_TX_CLK_DELAY_POS;

		rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2,
		MSCC_PHY_RGMII_CNTL, RGMII_RX_CLK_DELAY_MASK,
		MSCC_PHY_RGMII_CNTL,
		RGMII_RX_CLK_DELAY_MASK \| RGMII_TX_CLK_DELAY_MASK,
		reg_val);

		mutex_unlock(&phydev->lock);
		@@ -2076,6 +2089,30 @@ static int vsc85xx_probe(struct phy_device *phydev)

		/* Microsemi VSC85xx PHYs */
		static struct phy_driver vsc85xx_driver[] = {
		{
		.phy_id = PHY_ID_VSC8502,
		.name = "Microsemi GE VSC8502 SyncE",
		.phy_id_mask = 0xfffffff0,
		/* PHY_BASIC_FEATURES */
		.soft_reset = &genphy_soft_reset,
		.config_init = &vsc85xx_config_init,
		.config_aneg = &vsc85xx_config_aneg,
		.read_status = &vsc85xx_read_status,
		.ack_interrupt = &vsc85xx_ack_interrupt,
		.config_intr = &vsc85xx_config_intr,
		.suspend = &genphy_suspend,
		.resume = &genphy_resume,
		.probe = &vsc85xx_probe,
		.set_wol = &vsc85xx_wol_set,
		.get_wol = &vsc85xx_wol_get,
		.get_tunable = &vsc85xx_get_tunable,
		.set_tunable = &vsc85xx_set_tunable,
		.read_page = &vsc85xx_phy_read_page,
		.write_page = &vsc85xx_phy_write_page,
		.get_sset_count = &vsc85xx_get_sset_count,
		.get_strings = &vsc85xx_get_strings,
		.get_stats = &vsc85xx_get_stats,
		},
		{
		.phy_id = PHY_ID_VSC8504,
		.name = "Microsemi GE VSC8504 SyncE",

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