Commit b69337d3 authored by Kevin Hilman's avatar Kevin Hilman
Browse files

Merge tag 'clk-meson-v5.4-1' of git://github.com/BayLibre/clk-meson into v5.4/dt64 

Amlogic clock changes for v5.4

* Migrate to new clock description method
* Add DVFS support to g12

# gpg: Signature made Mon 12 Aug 2019 02:11:32 AM PDT
# gpg:                using RSA key F4E159AE18F3F56D5F1BB71BE6FC0F1C37F2DA85
# gpg: Good signature from "Jerome Brunet <jbrunet@baylibre.com>" [full]
# gpg:                 aka "Jerome Brunet <jerome@liltaz.com>" [full]
# gpg:                 aka "Jerome Brunet <jerome.brunet@gmail.com>" [full]

* tag 'clk-meson-v5.4-1' of git://github.com/BayLibre/clk-meson:
  clk: meson: g12a: expose CPUB clock ID for G12B
  clk: meson: g12a: add notifiers to handle cpu clock change
  clk: meson: add g12a cpu dynamic divider driver
  clk: core: introduce clk_hw_set_parent()
  clk: meson: remove clk input helper
  clk: meson: remove ee input bypass clocks
  clk: meson: clk-regmap: migrate to new parent description method
  clk: meson: meson8b: migrate to the new parent description method
  clk: meson: axg: migrate to the new parent description method
  clk: meson: gxbb: migrate to the new parent description method
  clk: meson: g12a: migrate to the new parent description method
  clk: meson: remove ao input bypass clocks
  clk: meson: axg-aoclk: migrate to the new parent description method
  clk: meson: gxbb-aoclk: migrate to the new parent description method
  clk: meson: g12a-aoclk: migrate to the new parent description method
  clk: meson: axg-audio: migrate to the new parent description method
  clk: meson: g12a: fix hifi typo in mali parent_names
parents e2fb6f7c 1d97657a

drivers/clk/clk.c

+6 −0
Original line number Diff line number Diff line
@@ -2487,6 +2487,12 @@ runtime_put: 
	return ret;

}



int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *parent)

{

	return clk_core_set_parent_nolock(hw->core, parent->core);

}

EXPORT_SYMBOL_GPL(clk_hw_set_parent);



/**

 * clk_set_parent - switch the parent of a mux clk

 * @clk: the mux clk whose input we are switching

drivers/clk/meson/Kconfig

+5 −6
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only

config COMMON_CLK_MESON_INPUT

	tristate



config COMMON_CLK_MESON_REGMAP

	tristate

	select REGMAP
@@ -33,13 +30,15 @@ config COMMON_CLK_MESON_VID_PLL_DIV 
config COMMON_CLK_MESON_AO_CLKC

	tristate

	select COMMON_CLK_MESON_REGMAP

	select COMMON_CLK_MESON_INPUT

	select RESET_CONTROLLER



config COMMON_CLK_MESON_EE_CLKC

	tristate

	select COMMON_CLK_MESON_REGMAP

	select COMMON_CLK_MESON_INPUT



config COMMON_CLK_MESON_CPU_DYNDIV

	tristate

	select COMMON_CLK_MESON_REGMAP



config COMMON_CLK_MESON8B

	bool
@@ -86,7 +85,6 @@ config COMMON_CLK_AXG 
config COMMON_CLK_AXG_AUDIO

	tristate "Meson AXG Audio Clock Controller Driver"

	depends on ARCH_MESON

	select COMMON_CLK_MESON_INPUT

	select COMMON_CLK_MESON_REGMAP

	select COMMON_CLK_MESON_PHASE

	select COMMON_CLK_MESON_SCLK_DIV
@@ -104,6 +102,7 @@ config COMMON_CLK_G12A 
	select COMMON_CLK_MESON_PLL

	select COMMON_CLK_MESON_AO_CLKC

	select COMMON_CLK_MESON_EE_CLKC

	select COMMON_CLK_MESON_CPU_DYNDIV

	select MFD_SYSCON

	help

	  Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2

drivers/clk/meson/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -2,9 +2,9 @@ 
# Amlogic clock drivers



obj-$(CONFIG_COMMON_CLK_MESON_AO_CLKC) += meson-aoclk.o

obj-$(CONFIG_COMMON_CLK_MESON_CPU_DYNDIV) += clk-cpu-dyndiv.o

obj-$(CONFIG_COMMON_CLK_MESON_DUALDIV) += clk-dualdiv.o

obj-$(CONFIG_COMMON_CLK_MESON_EE_CLKC) += meson-eeclk.o

obj-$(CONFIG_COMMON_CLK_MESON_INPUT) += clk-input.o

obj-$(CONFIG_COMMON_CLK_MESON_MPLL) += clk-mpll.o

obj-$(CONFIG_COMMON_CLK_MESON_PHASE) += clk-phase.o

obj-$(CONFIG_COMMON_CLK_MESON_PLL) += clk-pll.o

drivers/clk/meson/axg-aoclk.c

+37 −26
Original line number Diff line number Diff line
@@ -18,8 +18,6 @@ 
#include "clk-regmap.h"

#include "clk-dualdiv.h"



#define IN_PREFIX "ao-in-"



/*

 * AO Configuration Clock registers offsets

 * Register offsets from the data sheet must be multiplied by 4.
@@ -42,7 +40,9 @@ static struct clk_regmap axg_aoclk_##_name = { \ 
	.hw.init = &(struct clk_init_data) {				\

		.name =  "axg_ao_" #_name,				\

		.ops = &clk_regmap_gate_ops,				\

		.parent_names = (const char *[]){ IN_PREFIX "mpeg-clk" }, \

		.parent_data = &(const struct clk_parent_data) {	\

			.fw_name = "mpeg-clk",				\

		},							\

		.num_parents = 1,					\

		.flags = CLK_IGNORE_UNUSED,				\

	},								\
@@ -64,7 +64,9 @@ static struct clk_regmap axg_aoclk_cts_oscin = { 
	.hw.init = &(struct clk_init_data){

		.name = "cts_oscin",

		.ops = &clk_regmap_gate_ro_ops,

		.parent_names = (const char *[]){ IN_PREFIX "xtal" },

		.parent_data = &(const struct clk_parent_data) {

			.fw_name = "xtal",

		},

		.num_parents = 1,

	},

};
@@ -77,7 +79,9 @@ static struct clk_regmap axg_aoclk_32k_pre = { 
	.hw.init = &(struct clk_init_data){

		.name = "axg_ao_32k_pre",

		.ops = &clk_regmap_gate_ops,

		.parent_names = (const char *[]){ "cts_oscin" },

		.parent_hws = (const struct clk_hw *[]) {

			&axg_aoclk_cts_oscin.hw

		},

		.num_parents = 1,

	},

};
@@ -124,7 +128,9 @@ static struct clk_regmap axg_aoclk_32k_div = { 
	.hw.init = &(struct clk_init_data){

		.name = "axg_ao_32k_div",

		.ops = &meson_clk_dualdiv_ops,

		.parent_names = (const char *[]){ "axg_ao_32k_pre" },

		.parent_hws = (const struct clk_hw *[]) {

			&axg_aoclk_32k_pre.hw

		},

		.num_parents = 1,

	},

};
@@ -139,8 +145,10 @@ static struct clk_regmap axg_aoclk_32k_sel = { 
	.hw.init = &(struct clk_init_data){

		.name = "axg_ao_32k_sel",

		.ops = &clk_regmap_mux_ops,

		.parent_names = (const char *[]){ "axg_ao_32k_div",

						  "axg_ao_32k_pre" },

		.parent_hws = (const struct clk_hw *[]) {

			&axg_aoclk_32k_div.hw,

			&axg_aoclk_32k_pre.hw,

		},

		.num_parents = 2,

		.flags = CLK_SET_RATE_PARENT,

	},
@@ -154,7 +162,9 @@ static struct clk_regmap axg_aoclk_32k = { 
	.hw.init = &(struct clk_init_data){

		.name = "axg_ao_32k",

		.ops = &clk_regmap_gate_ops,

		.parent_names = (const char *[]){ "axg_ao_32k_sel" },

		.parent_hws = (const struct clk_hw *[]) {

			&axg_aoclk_32k_sel.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},
@@ -170,8 +180,10 @@ static struct clk_regmap axg_aoclk_cts_rtc_oscin = { 
	.hw.init = &(struct clk_init_data){

		.name = "axg_ao_cts_rtc_oscin",

		.ops = &clk_regmap_mux_ops,

		.parent_names = (const char *[]){ "axg_ao_32k",

						  IN_PREFIX "ext_32k-0" },

		.parent_data = (const struct clk_parent_data []) {

			{ .hw = &axg_aoclk_32k.hw },

			{ .fw_name = "ext_32k-0", },

		},

		.num_parents = 2,

		.flags = CLK_SET_RATE_PARENT,

	},
@@ -187,8 +199,10 @@ static struct clk_regmap axg_aoclk_clk81 = { 
	.hw.init = &(struct clk_init_data){

		.name = "axg_ao_clk81",

		.ops = &clk_regmap_mux_ro_ops,

		.parent_names = (const char *[]){ IN_PREFIX "mpeg-clk",

						  "axg_ao_cts_rtc_oscin"},

		.parent_data = (const struct clk_parent_data []) {

			{ .fw_name = "mpeg-clk", },

			{ .hw = &axg_aoclk_cts_rtc_oscin.hw },

		},

		.num_parents = 2,

		.flags = CLK_SET_RATE_PARENT,

	},
@@ -203,8 +217,10 @@ static struct clk_regmap axg_aoclk_saradc_mux = { 
	.hw.init = &(struct clk_init_data){

		.name = "axg_ao_saradc_mux",

		.ops = &clk_regmap_mux_ops,

		.parent_names = (const char *[]){ IN_PREFIX "xtal",

						  "axg_ao_clk81" },

		.parent_data = (const struct clk_parent_data []) {

			{ .fw_name = "xtal", },

			{ .hw = &axg_aoclk_clk81.hw },

		},

		.num_parents = 2,

	},

};
@@ -218,7 +234,9 @@ static struct clk_regmap axg_aoclk_saradc_div = { 
	.hw.init = &(struct clk_init_data){

		.name = "axg_ao_saradc_div",

		.ops = &clk_regmap_divider_ops,

		.parent_names = (const char *[]){ "axg_ao_saradc_mux" },

		.parent_hws = (const struct clk_hw *[]) {

			&axg_aoclk_saradc_mux.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},
@@ -232,7 +250,9 @@ static struct clk_regmap axg_aoclk_saradc_gate = { 
	.hw.init = &(struct clk_init_data){

		.name = "axg_ao_saradc_gate",

		.ops = &clk_regmap_gate_ops,

		.parent_names = (const char *[]){ "axg_ao_saradc_div" },

		.parent_hws = (const struct clk_hw *[]) {

			&axg_aoclk_saradc_div.hw

		},

		.num_parents = 1,

		.flags = CLK_SET_RATE_PARENT,

	},
@@ -290,12 +310,6 @@ static const struct clk_hw_onecell_data axg_aoclk_onecell_data = { 
	.num = NR_CLKS,

};



static const struct meson_aoclk_input axg_aoclk_inputs[] = {

	{ .name = "xtal",	.required = true  },

	{ .name = "mpeg-clk",	.required = true  },

	{ .name = "ext-32k-0",	.required = false },

};



static const struct meson_aoclk_data axg_aoclkc_data = {

	.reset_reg	= AO_RTI_GEN_CNTL_REG0,

	.num_reset	= ARRAY_SIZE(axg_aoclk_reset),
@@ -303,9 +317,6 @@ static const struct meson_aoclk_data axg_aoclkc_data = { 
	.num_clks	= ARRAY_SIZE(axg_aoclk_regmap),

	.clks		= axg_aoclk_regmap,

	.hw_data	= &axg_aoclk_onecell_data,

	.inputs		= axg_aoclk_inputs,

	.num_inputs	= ARRAY_SIZE(axg_aoclk_inputs),

	.input_prefix	= IN_PREFIX,

};



static const struct of_device_id axg_aoclkc_match_table[] = {

drivers/clk/meson/axg-audio.c

+120 −141
Original line number Diff line number Diff line
@@ -15,7 +15,6 @@ 
#include <linux/slab.h>



#include "axg-audio.h"

#include "clk-input.h"

#include "clk-regmap.h"

#include "clk-phase.h"

#include "sclk-div.h"
@@ -24,7 +23,7 @@ 
#define AUD_SLV_SCLK_COUNT	10

#define AUD_SLV_LRCLK_COUNT	10



#define AUD_GATE(_name, _reg, _bit, _pname, _iflags)			\

#define AUD_GATE(_name, _reg, _bit, _phws, _iflags)			\

struct clk_regmap aud_##_name = {					\

	.data = &(struct clk_regmap_gate_data){				\

		.offset = (_reg),					\
@@ -33,13 +32,13 @@ struct clk_regmap aud_##_name = { \ 
	.hw.init = &(struct clk_init_data) {				\

		.name = "aud_"#_name,					\

		.ops = &clk_regmap_gate_ops,				\

		.parent_names = (const char *[]){ _pname },		\

		.parent_hws = (const struct clk_hw *[]) { &_phws.hw },	\

		.num_parents = 1,					\

		.flags = CLK_DUTY_CYCLE_PARENT | (_iflags),		\

	},								\

}



#define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pnames, _iflags)	\

#define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags)	\

struct clk_regmap aud_##_name = {					\

	.data = &(struct clk_regmap_mux_data){				\

		.offset = (_reg),					\
@@ -50,13 +49,13 @@ struct clk_regmap aud_##_name = { \ 
	.hw.init = &(struct clk_init_data){				\

		.name = "aud_"#_name,					\

		.ops = &clk_regmap_mux_ops,				\

		.parent_names = (_pnames),				\

		.num_parents = ARRAY_SIZE(_pnames),			\

		.parent_data = _pdata,					\

		.num_parents = ARRAY_SIZE(_pdata),			\

		.flags = CLK_DUTY_CYCLE_PARENT | (_iflags),		\

	},								\

}



#define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags)	\

#define AUD_DIV(_name, _reg, _shift, _width, _dflags, _phws, _iflags)	\

struct clk_regmap aud_##_name = {					\

	.data = &(struct clk_regmap_div_data){				\

		.offset = (_reg),					\
@@ -67,15 +66,27 @@ struct clk_regmap aud_##_name = { \ 
	.hw.init = &(struct clk_init_data){				\

		.name = "aud_"#_name,					\

		.ops = &clk_regmap_divider_ops,				\

		.parent_names = (const char *[]) { _pname },		\

		.parent_hws = (const struct clk_hw *[]) { &_phws.hw },	\

		.num_parents = 1,					\

		.flags = (_iflags),					\

	},								\

}



#define AUD_PCLK_GATE(_name, _bit)				\

	AUD_GATE(_name, AUDIO_CLK_GATE_EN, _bit, "audio_pclk", 0)



struct clk_regmap aud_##_name = {					\

	.data = &(struct clk_regmap_gate_data){				\

		.offset = (AUDIO_CLK_GATE_EN),				\

		.bit_idx = (_bit),					\

	},								\

	.hw.init = &(struct clk_init_data) {				\

		.name = "aud_"#_name,					\

		.ops = &clk_regmap_gate_ops,				\

		.parent_data = &(const struct clk_parent_data) {	\

			.fw_name = "pclk",				\

		},							\

		.num_parents = 1,					\

	},								\

}

/* Audio peripheral clocks */

static AUD_PCLK_GATE(ddr_arb,	   0);

static AUD_PCLK_GATE(pdm,	   1);
@@ -100,14 +111,20 @@ static AUD_PCLK_GATE(power_detect, 19); 
static AUD_PCLK_GATE(spdifout_b,   21);



/* Audio Master Clocks */

static const char * const mst_mux_parent_names[] = {

	"aud_mst_in0", "aud_mst_in1", "aud_mst_in2", "aud_mst_in3",

	"aud_mst_in4", "aud_mst_in5", "aud_mst_in6", "aud_mst_in7",

static const struct clk_parent_data mst_mux_parent_data[] = {

	{ .fw_name = "mst_in0", },

	{ .fw_name = "mst_in1", },

	{ .fw_name = "mst_in2", },

	{ .fw_name = "mst_in3", },

	{ .fw_name = "mst_in4", },

	{ .fw_name = "mst_in5", },

	{ .fw_name = "mst_in6", },

	{ .fw_name = "mst_in7", },

};



#define AUD_MST_MUX(_name, _reg, _flag)				\

	AUD_MUX(_name##_sel, _reg, 0x7, 24, _flag,		\

		mst_mux_parent_names, CLK_SET_RATE_PARENT)

		mst_mux_parent_data, 0)



#define AUD_MST_MCLK_MUX(_name, _reg)				\

	AUD_MST_MUX(_name, _reg, CLK_MUX_ROUND_CLOSEST)
@@ -129,7 +146,7 @@ static AUD_MST_MCLK_MUX(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL); 


#define AUD_MST_DIV(_name, _reg, _flag)				\

	AUD_DIV(_name##_div, _reg, 0, 16, _flag,		\

		    "aud_"#_name"_sel", CLK_SET_RATE_PARENT)	\

		    aud_##_name##_sel, CLK_SET_RATE_PARENT)	\



#define AUD_MST_MCLK_DIV(_name, _reg)				\

	AUD_MST_DIV(_name, _reg, CLK_DIVIDER_ROUND_CLOSEST)
@@ -150,7 +167,7 @@ static AUD_MST_SYS_DIV(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1); 
static AUD_MST_MCLK_DIV(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);



#define AUD_MST_MCLK_GATE(_name, _reg)				\

	AUD_GATE(_name, _reg, 31,  "aud_"#_name"_div",	\

	AUD_GATE(_name, _reg, 31,  aud_##_name##_div,		\

		 CLK_SET_RATE_PARENT)



static AUD_MST_MCLK_GATE(mst_a_mclk,   AUDIO_MCLK_A_CTRL);
@@ -168,7 +185,7 @@ static AUD_MST_MCLK_GATE(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL); 
/* Sample Clocks */

#define AUD_MST_SCLK_PRE_EN(_name, _reg)			\

	AUD_GATE(mst_##_name##_sclk_pre_en, _reg, 31,		\

		 "aud_mst_"#_name"_mclk", 0)

		 aud_mst_##_name##_mclk, 0)



static AUD_MST_SCLK_PRE_EN(a, AUDIO_MST_A_SCLK_CTRL0);

static AUD_MST_SCLK_PRE_EN(b, AUDIO_MST_B_SCLK_CTRL0);
@@ -178,7 +195,7 @@ static AUD_MST_SCLK_PRE_EN(e, AUDIO_MST_E_SCLK_CTRL0); 
static AUD_MST_SCLK_PRE_EN(f, AUDIO_MST_F_SCLK_CTRL0);



#define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width,		\

			 _hi_shift, _hi_width, _pname, _iflags)		\

			 _hi_shift, _hi_width, _phws, _iflags)		\

struct clk_regmap aud_##_name = {					\

	.data = &(struct meson_sclk_div_data) {				\

		.div = {						\
@@ -195,7 +212,7 @@ struct clk_regmap aud_##_name = { \ 
	.hw.init = &(struct clk_init_data) {				\

		.name = "aud_"#_name,					\

		.ops = &meson_sclk_div_ops,				\

		.parent_names = (const char *[]) { _pname },		\

		.parent_hws = (const struct clk_hw *[]) { &_phws.hw },	\

		.num_parents = 1,					\

		.flags = (_iflags),					\

	},								\
@@ -203,7 +220,7 @@ struct clk_regmap aud_##_name = { \ 


#define AUD_MST_SCLK_DIV(_name, _reg)					\

	AUD_SCLK_DIV(mst_##_name##_sclk_div, _reg, 20, 10, 0, 0,	\

		     "aud_mst_"#_name"_sclk_pre_en",			\

		     aud_mst_##_name##_sclk_pre_en,			\

		     CLK_SET_RATE_PARENT)



static AUD_MST_SCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
@@ -215,7 +232,7 @@ static AUD_MST_SCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0); 


#define AUD_MST_SCLK_POST_EN(_name, _reg)				\

	AUD_GATE(mst_##_name##_sclk_post_en, _reg, 30,			\

		 "aud_mst_"#_name"_sclk_div", CLK_SET_RATE_PARENT)

		 aud_mst_##_name##_sclk_div, CLK_SET_RATE_PARENT)



static AUD_MST_SCLK_POST_EN(a, AUDIO_MST_A_SCLK_CTRL0);

static AUD_MST_SCLK_POST_EN(b, AUDIO_MST_B_SCLK_CTRL0);
@@ -225,7 +242,7 @@ static AUD_MST_SCLK_POST_EN(e, AUDIO_MST_E_SCLK_CTRL0); 
static AUD_MST_SCLK_POST_EN(f, AUDIO_MST_F_SCLK_CTRL0);



#define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2,	\

			 _pname, _iflags)				\

			 _phws, _iflags)				\

struct clk_regmap aud_##_name = {					\

	.data = &(struct meson_clk_triphase_data) {			\

		.ph0 = {						\
@@ -247,7 +264,7 @@ struct clk_regmap aud_##_name = { \ 
	.hw.init = &(struct clk_init_data) {				\

		.name = "aud_"#_name,					\

		.ops = &meson_clk_triphase_ops,				\

		.parent_names = (const char *[]) { _pname },		\

		.parent_hws = (const struct clk_hw *[]) { &_phws.hw },	\

		.num_parents = 1,					\

		.flags = CLK_DUTY_CYCLE_PARENT | (_iflags),		\

	},								\
@@ -255,7 +272,7 @@ struct clk_regmap aud_##_name = { \ 


#define AUD_MST_SCLK(_name, _reg)					\

	AUD_TRIPHASE(mst_##_name##_sclk, _reg, 1, 0, 2, 4,		\

		     "aud_mst_"#_name"_sclk_post_en", CLK_SET_RATE_PARENT)

		     aud_mst_##_name##_sclk_post_en, CLK_SET_RATE_PARENT)



static AUD_MST_SCLK(a, AUDIO_MST_A_SCLK_CTRL1);

static AUD_MST_SCLK(b, AUDIO_MST_B_SCLK_CTRL1);
@@ -266,7 +283,7 @@ static AUD_MST_SCLK(f, AUDIO_MST_F_SCLK_CTRL1); 


#define AUD_MST_LRCLK_DIV(_name, _reg)					\

	AUD_SCLK_DIV(mst_##_name##_lrclk_div, _reg, 0, 10, 10, 10,	\

		     "aud_mst_"#_name"_sclk_post_en", 0)		\

		     aud_mst_##_name##_sclk_post_en, 0)			\



static AUD_MST_LRCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);

static AUD_MST_LRCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
@@ -277,7 +294,7 @@ static AUD_MST_LRCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0); 


#define AUD_MST_LRCLK(_name, _reg)					\

	AUD_TRIPHASE(mst_##_name##_lrclk, _reg, 1, 1, 3, 5,		\

		     "aud_mst_"#_name"_lrclk_div", CLK_SET_RATE_PARENT)

		     aud_mst_##_name##_lrclk_div, CLK_SET_RATE_PARENT)



static AUD_MST_LRCLK(a, AUDIO_MST_A_SCLK_CTRL1);

static AUD_MST_LRCLK(b, AUDIO_MST_B_SCLK_CTRL1);
@@ -286,19 +303,29 @@ static AUD_MST_LRCLK(d, AUDIO_MST_D_SCLK_CTRL1); 
static AUD_MST_LRCLK(e, AUDIO_MST_E_SCLK_CTRL1);

static AUD_MST_LRCLK(f, AUDIO_MST_F_SCLK_CTRL1);



static const char * const tdm_sclk_parent_names[] = {

	"aud_mst_a_sclk", "aud_mst_b_sclk", "aud_mst_c_sclk",

	"aud_mst_d_sclk", "aud_mst_e_sclk", "aud_mst_f_sclk",

	"aud_slv_sclk0", "aud_slv_sclk1", "aud_slv_sclk2",

	"aud_slv_sclk3", "aud_slv_sclk4", "aud_slv_sclk5",

	"aud_slv_sclk6", "aud_slv_sclk7", "aud_slv_sclk8",

	"aud_slv_sclk9"

static const struct clk_parent_data tdm_sclk_parent_data[] = {

	{ .hw = &aud_mst_a_sclk.hw, },

	{ .hw = &aud_mst_b_sclk.hw, },

	{ .hw = &aud_mst_c_sclk.hw, },

	{ .hw = &aud_mst_d_sclk.hw, },

	{ .hw = &aud_mst_e_sclk.hw, },

	{ .hw = &aud_mst_f_sclk.hw, },

	{ .fw_name = "slv_sclk0", },

	{ .fw_name = "slv_sclk1", },

	{ .fw_name = "slv_sclk2", },

	{ .fw_name = "slv_sclk3", },

	{ .fw_name = "slv_sclk4", },

	{ .fw_name = "slv_sclk5", },

	{ .fw_name = "slv_sclk6", },

	{ .fw_name = "slv_sclk7", },

	{ .fw_name = "slv_sclk8", },

	{ .fw_name = "slv_sclk9", },

};



#define AUD_TDM_SCLK_MUX(_name, _reg)				\

	AUD_MUX(tdm##_name##_sclk_sel, _reg, 0xf, 24,		\

		    CLK_MUX_ROUND_CLOSEST,			\

		    tdm_sclk_parent_names, 0)

		    tdm_sclk_parent_data, 0)



static AUD_TDM_SCLK_MUX(in_a,  AUDIO_CLK_TDMIN_A_CTRL);

static AUD_TDM_SCLK_MUX(in_b,  AUDIO_CLK_TDMIN_B_CTRL);
@@ -310,7 +337,7 @@ static AUD_TDM_SCLK_MUX(out_c, AUDIO_CLK_TDMOUT_C_CTRL); 


#define AUD_TDM_SCLK_PRE_EN(_name, _reg)				\

	AUD_GATE(tdm##_name##_sclk_pre_en, _reg, 31,			\

		 "aud_tdm"#_name"_sclk_sel", CLK_SET_RATE_PARENT)

		 aud_tdm##_name##_sclk_sel, CLK_SET_RATE_PARENT)



static AUD_TDM_SCLK_PRE_EN(in_a,  AUDIO_CLK_TDMIN_A_CTRL);

static AUD_TDM_SCLK_PRE_EN(in_b,  AUDIO_CLK_TDMIN_B_CTRL);
@@ -322,7 +349,7 @@ static AUD_TDM_SCLK_PRE_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL); 


#define AUD_TDM_SCLK_POST_EN(_name, _reg)				\

	AUD_GATE(tdm##_name##_sclk_post_en, _reg, 30,			\

		 "aud_tdm"#_name"_sclk_pre_en", CLK_SET_RATE_PARENT)

		 aud_tdm##_name##_sclk_pre_en, CLK_SET_RATE_PARENT)



static AUD_TDM_SCLK_POST_EN(in_a,  AUDIO_CLK_TDMIN_A_CTRL);

static AUD_TDM_SCLK_POST_EN(in_b,  AUDIO_CLK_TDMIN_B_CTRL);
@@ -344,8 +371,9 @@ static AUD_TDM_SCLK_POST_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL); 
	.hw.init = &(struct clk_init_data) {				\

		.name = "aud_tdm"#_name"_sclk",				\

		.ops = &meson_clk_phase_ops,				\

		.parent_names = (const char *[])			\

		{ "aud_tdm"#_name"_sclk_post_en" },			\

		.parent_hws = (const struct clk_hw *[]) {		\

			&aud_tdm##_name##_sclk_post_en.hw		\

		},							\

		.num_parents = 1,					\

		.flags = CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT,	\

	},								\
@@ -359,19 +387,29 @@ static AUD_TDM_SCLK(out_a, AUDIO_CLK_TDMOUT_A_CTRL); 
static AUD_TDM_SCLK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);

static AUD_TDM_SCLK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);



static const char * const tdm_lrclk_parent_names[] = {

	"aud_mst_a_lrclk", "aud_mst_b_lrclk", "aud_mst_c_lrclk",

	"aud_mst_d_lrclk", "aud_mst_e_lrclk", "aud_mst_f_lrclk",

	"aud_slv_lrclk0", "aud_slv_lrclk1", "aud_slv_lrclk2",

	"aud_slv_lrclk3", "aud_slv_lrclk4", "aud_slv_lrclk5",

	"aud_slv_lrclk6", "aud_slv_lrclk7", "aud_slv_lrclk8",

	"aud_slv_lrclk9"

static const struct clk_parent_data tdm_lrclk_parent_data[] = {

	{ .hw = &aud_mst_a_lrclk.hw, },

	{ .hw = &aud_mst_b_lrclk.hw, },

	{ .hw = &aud_mst_c_lrclk.hw, },

	{ .hw = &aud_mst_d_lrclk.hw, },

	{ .hw = &aud_mst_e_lrclk.hw, },

	{ .hw = &aud_mst_f_lrclk.hw, },

	{ .fw_name = "slv_lrclk0", },

	{ .fw_name = "slv_lrclk1", },

	{ .fw_name = "slv_lrclk2", },

	{ .fw_name = "slv_lrclk3", },

	{ .fw_name = "slv_lrclk4", },

	{ .fw_name = "slv_lrclk5", },

	{ .fw_name = "slv_lrclk6", },

	{ .fw_name = "slv_lrclk7", },

	{ .fw_name = "slv_lrclk8", },

	{ .fw_name = "slv_lrclk9", },

};



#define AUD_TDM_LRLCK(_name, _reg)			\

	AUD_MUX(tdm##_name##_lrclk, _reg, 0xf, 20,	\

		CLK_MUX_ROUND_CLOSEST,			\

		tdm_lrclk_parent_names, 0)

		tdm_lrclk_parent_data, 0)



static AUD_TDM_LRLCK(in_a,  AUDIO_CLK_TDMIN_A_CTRL);

static AUD_TDM_LRLCK(in_b,  AUDIO_CLK_TDMIN_B_CTRL);
@@ -386,39 +424,51 @@ static AUD_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL); 
	AUD_MUX(tdm_##_name, _reg, 0x7, _shift, 0, _parents,	\

		CLK_SET_RATE_NO_REPARENT)



static const char * const mclk_pad_ctrl_parent_names[] = {

	"aud_mst_a_mclk", "aud_mst_b_mclk", "aud_mst_c_mclk",

	"aud_mst_d_mclk", "aud_mst_e_mclk", "aud_mst_f_mclk",

static const struct clk_parent_data mclk_pad_ctrl_parent_data[] = {

	{ .hw = &aud_mst_a_mclk.hw },

	{ .hw = &aud_mst_b_mclk.hw },

	{ .hw = &aud_mst_c_mclk.hw },

	{ .hw = &aud_mst_d_mclk.hw },

	{ .hw = &aud_mst_e_mclk.hw },

	{ .hw = &aud_mst_f_mclk.hw },

};



static AUD_TDM_PAD_CTRL(mclk_pad_0, AUDIO_MST_PAD_CTRL0, 0,

			mclk_pad_ctrl_parent_names);

			mclk_pad_ctrl_parent_data);

static AUD_TDM_PAD_CTRL(mclk_pad_1, AUDIO_MST_PAD_CTRL0, 4,

			mclk_pad_ctrl_parent_names);



static const char * const lrclk_pad_ctrl_parent_names[] = {

	"aud_mst_a_lrclk", "aud_mst_b_lrclk", "aud_mst_c_lrclk",

	"aud_mst_d_lrclk", "aud_mst_e_lrclk", "aud_mst_f_lrclk",

			mclk_pad_ctrl_parent_data);



static const struct clk_parent_data lrclk_pad_ctrl_parent_data[] = {

	{ .hw = &aud_mst_a_lrclk.hw },

	{ .hw = &aud_mst_b_lrclk.hw },

	{ .hw = &aud_mst_c_lrclk.hw },

	{ .hw = &aud_mst_d_lrclk.hw },

	{ .hw = &aud_mst_e_lrclk.hw },

	{ .hw = &aud_mst_f_lrclk.hw },

};



static AUD_TDM_PAD_CTRL(lrclk_pad_0, AUDIO_MST_PAD_CTRL1, 16,

			lrclk_pad_ctrl_parent_names);

			lrclk_pad_ctrl_parent_data);

static AUD_TDM_PAD_CTRL(lrclk_pad_1, AUDIO_MST_PAD_CTRL1, 20,

			lrclk_pad_ctrl_parent_names);

			lrclk_pad_ctrl_parent_data);

static AUD_TDM_PAD_CTRL(lrclk_pad_2, AUDIO_MST_PAD_CTRL1, 24,

			lrclk_pad_ctrl_parent_names);



static const char * const sclk_pad_ctrl_parent_names[] = {

	"aud_mst_a_sclk", "aud_mst_b_sclk", "aud_mst_c_sclk",

	"aud_mst_d_sclk", "aud_mst_e_sclk", "aud_mst_f_sclk",

			lrclk_pad_ctrl_parent_data);



static const struct clk_parent_data sclk_pad_ctrl_parent_data[] = {

	{ .hw = &aud_mst_a_sclk.hw },

	{ .hw = &aud_mst_b_sclk.hw },

	{ .hw = &aud_mst_c_sclk.hw },

	{ .hw = &aud_mst_d_sclk.hw },

	{ .hw = &aud_mst_e_sclk.hw },

	{ .hw = &aud_mst_f_sclk.hw },

};



static AUD_TDM_PAD_CTRL(sclk_pad_0, AUDIO_MST_PAD_CTRL1, 0,

			sclk_pad_ctrl_parent_names);

			sclk_pad_ctrl_parent_data);

static AUD_TDM_PAD_CTRL(sclk_pad_1, AUDIO_MST_PAD_CTRL1, 4,

			sclk_pad_ctrl_parent_names);

			sclk_pad_ctrl_parent_data);

static AUD_TDM_PAD_CTRL(sclk_pad_2, AUDIO_MST_PAD_CTRL1, 8,

			sclk_pad_ctrl_parent_names);

			sclk_pad_ctrl_parent_data);



/*

 * Array of all clocks provided by this provider
@@ -868,54 +918,6 @@ static int devm_clk_get_enable(struct device *dev, char *id) 
	return 0;

}



static int axg_register_clk_hw_input(struct device *dev,

				     const char *name)

{

	char *clk_name;

	struct clk_hw *hw;

	int err = 0;



	clk_name = kasprintf(GFP_KERNEL, "aud_%s", name);

	if (!clk_name)

		return -ENOMEM;



	hw = meson_clk_hw_register_input(dev, name, clk_name, 0);

	if (IS_ERR(hw)) {

		/* It is ok if an input clock is missing */

		if (PTR_ERR(hw) == -ENOENT) {

			dev_dbg(dev, "%s not provided", name);

		} else {

			err = PTR_ERR(hw);

			if (err != -EPROBE_DEFER)

				dev_err(dev, "failed to get %s clock", name);

		}

	}



	kfree(clk_name);

	return err;

}



static int axg_register_clk_hw_inputs(struct device *dev,

				      const char *basename,

				      unsigned int count)

{

	char *name;

	int i, ret;



	for (i = 0; i < count; i++) {

		name = kasprintf(GFP_KERNEL, "%s%d", basename, i);

		if (!name)

			return -ENOMEM;



		ret = axg_register_clk_hw_input(dev, name);

		kfree(name);

		if (ret)

			return ret;

	}



	return 0;

}



static const struct regmap_config axg_audio_regmap_cfg = {

	.reg_bits	= 32,

	.val_bits	= 32,
@@ -963,29 +965,6 @@ static int axg_audio_clkc_probe(struct platform_device *pdev) 
		return ret;

	}



	/* Register the peripheral input clock */

	hw = meson_clk_hw_register_input(dev, "pclk", "audio_pclk", 0);

	if (IS_ERR(hw))

		return PTR_ERR(hw);



	/* Register optional input master clocks */

	ret = axg_register_clk_hw_inputs(dev, "mst_in",

					 AUD_MST_IN_COUNT);

	if (ret)

		return ret;



	/* Register optional input slave sclks */

	ret = axg_register_clk_hw_inputs(dev, "slv_sclk",

					 AUD_SLV_SCLK_COUNT);

	if (ret)

		return ret;



	/* Register optional input slave lrclks */

	ret = axg_register_clk_hw_inputs(dev, "slv_lrclk",

					 AUD_SLV_LRCLK_COUNT);

	if (ret)

		return ret;



	/* Populate regmap for the regmap backed clocks */

	for (i = 0; i < ARRAY_SIZE(aud_clk_regmaps); i++)

		aud_clk_regmaps[i]->map = map;

CRA Git | Maintained and supported by SUSTech CRA and CCSE