Merge branch 'next' of git://people.freedesktop.org/~deathsimple/linux into drm-next (b68bdc1b) · Commits · 戴 / test

drivers/gpu/drm/radeon/atombios_crtc.c

+9 −13

Original line number	Diff line number	Diff line
		@@ -457,22 +457,18 @@ static void atombios_crtc_program_ss(struct radeon_device *rdev,
		switch (pll_id) {
		case ATOM_PPLL1:
		args.v3.ucSpreadSpectrumType \|= ATOM_PPLL_SS_TYPE_V3_P1PLL;
		args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
		args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
		break;
		case ATOM_PPLL2:
		args.v3.ucSpreadSpectrumType \|= ATOM_PPLL_SS_TYPE_V3_P2PLL;
		args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
		args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
		break;
		case ATOM_DCPLL:
		args.v3.ucSpreadSpectrumType \|= ATOM_PPLL_SS_TYPE_V3_DCPLL;
		args.v3.usSpreadSpectrumAmount = cpu_to_le16(0);
		args.v3.usSpreadSpectrumStep = cpu_to_le16(0);
		break;
		case ATOM_PPLL_INVALID:
		return;
		}
		args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
		args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
		args.v3.ucEnable = enable;
		if ((ss->percentage == 0) \|\| (ss->type & ATOM_EXTERNAL_SS_MASK) \|\| ASIC_IS_DCE61(rdev))
		args.v3.ucEnable = ATOM_DISABLE;
		@@ -482,22 +478,18 @@ static void atombios_crtc_program_ss(struct radeon_device *rdev,
		switch (pll_id) {
		case ATOM_PPLL1:
		args.v2.ucSpreadSpectrumType \|= ATOM_PPLL_SS_TYPE_V2_P1PLL;
		args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
		args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
		break;
		case ATOM_PPLL2:
		args.v2.ucSpreadSpectrumType \|= ATOM_PPLL_SS_TYPE_V2_P2PLL;
		args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
		args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
		break;
		case ATOM_DCPLL:
		args.v2.ucSpreadSpectrumType \|= ATOM_PPLL_SS_TYPE_V2_DCPLL;
		args.v2.usSpreadSpectrumAmount = cpu_to_le16(0);
		args.v2.usSpreadSpectrumStep = cpu_to_le16(0);
		break;
		case ATOM_PPLL_INVALID:
		return;
		}
		args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
		args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
		args.v2.ucEnable = enable;
		if ((ss->percentage == 0) \|\| (ss->type & ATOM_EXTERNAL_SS_MASK) \|\| ASIC_IS_DCE41(rdev))
		args.v2.ucEnable = ATOM_DISABLE;
		@@ -1539,7 +1531,11 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
		* crtc virtual pixel clock.
		*/
		if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {
		if (ASIC_IS_DCE5(rdev) \|\| rdev->clock.dp_extclk)
		if (ASIC_IS_DCE5(rdev))
		return ATOM_DCPLL;
		else if (ASIC_IS_DCE6(rdev))
		return ATOM_PPLL0;
		else if (rdev->clock.dp_extclk)
		return ATOM_PPLL_INVALID;
		}
		}

drivers/gpu/drm/radeon/evergreen.c

+129 −1

Original line number	Diff line number	Diff line
		@@ -99,6 +99,14 @@ void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
		}
		}

		/**
		* dce4_wait_for_vblank - vblank wait asic callback.
		*
		* @rdev: radeon_device pointer
		* @crtc: crtc to wait for vblank on
		*
		* Wait for vblank on the requested crtc (evergreen+).
		*/
		void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc)
		{
		struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
		@@ -118,18 +126,49 @@ void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc)
		}
		}

		/**
		* radeon_irq_kms_pflip_irq_get - pre-pageflip callback.
		*
		* @rdev: radeon_device pointer
		* @crtc: crtc to prepare for pageflip on
		*
		* Pre-pageflip callback (evergreen+).
		* Enables the pageflip irq (vblank irq).
		*/
		void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
		{
		/* enable the pflip int */
		radeon_irq_kms_pflip_irq_get(rdev, crtc);
		}

		/**
		* evergreen_post_page_flip - pos-pageflip callback.
		*
		* @rdev: radeon_device pointer
		* @crtc: crtc to cleanup pageflip on
		*
		* Post-pageflip callback (evergreen+).
		* Disables the pageflip irq (vblank irq).
		*/
		void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
		{
		/* disable the pflip int */
		radeon_irq_kms_pflip_irq_put(rdev, crtc);
		}

		/**
		* evergreen_page_flip - pageflip callback.
		*
		* @rdev: radeon_device pointer
		* @crtc_id: crtc to cleanup pageflip on
		* @crtc_base: new address of the crtc (GPU MC address)
		*
		* Does the actual pageflip (evergreen+).
		* During vblank we take the crtc lock and wait for the update_pending
		* bit to go high, when it does, we release the lock, and allow the
		* double buffered update to take place.
		* Returns the current update pending status.
		*/
		u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
		{
		struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
		@@ -214,6 +253,15 @@ int sumo_get_temp(struct radeon_device *rdev)
		return actual_temp * 1000;
		}

		/**
		* sumo_pm_init_profile - Initialize power profiles callback.
		*
		* @rdev: radeon_device pointer
		*
		* Initialize the power states used in profile mode
		* (sumo, trinity, SI).
		* Used for profile mode only.
		*/
		void sumo_pm_init_profile(struct radeon_device *rdev)
		{
		int idx;
		@@ -265,6 +313,14 @@ void sumo_pm_init_profile(struct radeon_device *rdev)
		rdev->pm.power_state[idx].num_clock_modes - 1;
		}

		/**
		* evergreen_pm_misc - set additional pm hw parameters callback.
		*
		* @rdev: radeon_device pointer
		*
		* Set non-clock parameters associated with a power state
		* (voltage, etc.) (evergreen+).
		*/
		void evergreen_pm_misc(struct radeon_device *rdev)
		{
		int req_ps_idx = rdev->pm.requested_power_state_index;
		@@ -292,6 +348,13 @@ void evergreen_pm_misc(struct radeon_device *rdev)
		}
		}

		/**
		* evergreen_pm_prepare - pre-power state change callback.
		*
		* @rdev: radeon_device pointer
		*
		* Prepare for a power state change (evergreen+).
		*/
		void evergreen_pm_prepare(struct radeon_device *rdev)
		{
		struct drm_device *ddev = rdev->ddev;
		@@ -310,6 +373,13 @@ void evergreen_pm_prepare(struct radeon_device *rdev)
		}
		}

		/**
		* evergreen_pm_finish - post-power state change callback.
		*
		* @rdev: radeon_device pointer
		*
		* Clean up after a power state change (evergreen+).
		*/
		void evergreen_pm_finish(struct radeon_device *rdev)
		{
		struct drm_device *ddev = rdev->ddev;
		@@ -328,6 +398,15 @@ void evergreen_pm_finish(struct radeon_device *rdev)
		}
		}

		/**
		* evergreen_hpd_sense - hpd sense callback.
		*
		* @rdev: radeon_device pointer
		* @hpd: hpd (hotplug detect) pin
		*
		* Checks if a digital monitor is connected (evergreen+).
		* Returns true if connected, false if not connected.
		*/
		bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
		{
		bool connected = false;
		@@ -364,6 +443,14 @@ bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
		return connected;
		}

		/**
		* evergreen_hpd_set_polarity - hpd set polarity callback.
		*
		* @rdev: radeon_device pointer
		* @hpd: hpd (hotplug detect) pin
		*
		* Set the polarity of the hpd pin (evergreen+).
		*/
		void evergreen_hpd_set_polarity(struct radeon_device *rdev,
		enum radeon_hpd_id hpd)
		{
		@@ -424,6 +511,14 @@ void evergreen_hpd_set_polarity(struct radeon_device *rdev,
		}
		}

		/**
		* evergreen_hpd_init - hpd setup callback.
		*
		* @rdev: radeon_device pointer
		*
		* Setup the hpd pins used by the card (evergreen+).
		* Enable the pin, set the polarity, and enable the hpd interrupts.
		*/
		void evergreen_hpd_init(struct radeon_device *rdev)
		{
		struct drm_device *dev = rdev->ddev;
		@@ -462,6 +557,14 @@ void evergreen_hpd_init(struct radeon_device *rdev)
		radeon_irq_kms_enable_hpd(rdev, enabled);
		}

		/**
		* evergreen_hpd_fini - hpd tear down callback.
		*
		* @rdev: radeon_device pointer
		*
		* Tear down the hpd pins used by the card (evergreen+).
		* Disable the hpd interrupts.
		*/
		void evergreen_hpd_fini(struct radeon_device *rdev)
		{
		struct drm_device *dev = rdev->ddev;
		@@ -925,6 +1028,14 @@ static void evergreen_program_watermarks(struct radeon_device *rdev,

		}

		/**
		* evergreen_bandwidth_update - update display watermarks callback.
		*
		* @rdev: radeon_device pointer
		*
		* Update the display watermarks based on the requested mode(s)
		* (evergreen+).
		*/
		void evergreen_bandwidth_update(struct radeon_device *rdev)
		{
		struct drm_display_mode *mode0 = NULL;
		@@ -948,6 +1059,15 @@ void evergreen_bandwidth_update(struct radeon_device *rdev)
		}
		}

		/**
		* evergreen_mc_wait_for_idle - wait for MC idle callback.
		*
		* @rdev: radeon_device pointer
		*
		* Wait for the MC (memory controller) to be idle.
		* (evergreen+).
		* Returns 0 if the MC is idle, -1 if not.
		*/
		int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
		{
		unsigned i;
		@@ -1364,17 +1484,25 @@ void evergreen_mc_program(struct radeon_device *rdev)
		void evergreen_ring_ib_execute(struct radeon_device rdev, struct radeon_ib ib)
		{
		struct radeon_ring *ring = &rdev->ring[ib->ring];
		u32 next_rptr;

		/* set to DX10/11 mode */
		radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
		radeon_ring_write(ring, 1);

		if (ring->rptr_save_reg) {
		uint32_t next_rptr = ring->wptr + 3 + 4;
		next_rptr = ring->wptr + 3 + 4;
		radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
		radeon_ring_write(ring, ((ring->rptr_save_reg -
		PACKET3_SET_CONFIG_REG_START) >> 2));
		radeon_ring_write(ring, next_rptr);
		} else if (rdev->wb.enabled) {
		next_rptr = ring->wptr + 5 + 4;
		radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
		radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
		radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) \| (1 << 18));
		radeon_ring_write(ring, next_rptr);
		radeon_ring_write(ring, 0);
		}

		radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));

drivers/gpu/drm/radeon/r100.c

+140 −4

Original line number	Diff line number	Diff line
		@@ -65,6 +65,19 @@ MODULE_FIRMWARE(FIRMWARE_R520);

		#include "r100_track.h"

		/* This files gather functions specifics to:
		* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
		* and others in some cases.
		*/

		/**
		* r100_wait_for_vblank - vblank wait asic callback.
		*
		* @rdev: radeon_device pointer
		* @crtc: crtc to wait for vblank on
		*
		* Wait for vblank on the requested crtc (r1xx-r4xx).
		*/
		void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
		{
		struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
		@@ -99,22 +112,49 @@ void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
		}
		}

		/* This files gather functions specifics to:
		* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
		/**
		* r100_pre_page_flip - pre-pageflip callback.
		*
		* @rdev: radeon_device pointer
		* @crtc: crtc to prepare for pageflip on
		*
		* Pre-pageflip callback (r1xx-r4xx).
		* Enables the pageflip irq (vblank irq).
		*/

		void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
		{
		/* enable the pflip int */
		radeon_irq_kms_pflip_irq_get(rdev, crtc);
		}

		/**
		* r100_post_page_flip - pos-pageflip callback.
		*
		* @rdev: radeon_device pointer
		* @crtc: crtc to cleanup pageflip on
		*
		* Post-pageflip callback (r1xx-r4xx).
		* Disables the pageflip irq (vblank irq).
		*/
		void r100_post_page_flip(struct radeon_device *rdev, int crtc)
		{
		/* disable the pflip int */
		radeon_irq_kms_pflip_irq_put(rdev, crtc);
		}

		/**
		* r100_page_flip - pageflip callback.
		*
		* @rdev: radeon_device pointer
		* @crtc_id: crtc to cleanup pageflip on
		* @crtc_base: new address of the crtc (GPU MC address)
		*
		* Does the actual pageflip (r1xx-r4xx).
		* During vblank we take the crtc lock and wait for the update_pending
		* bit to go high, when it does, we release the lock, and allow the
		* double buffered update to take place.
		* Returns the current update pending status.
		*/
		u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
		{
		struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
		@@ -141,6 +181,15 @@ u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
		return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
		}

		/**
		* r100_pm_get_dynpm_state - look up dynpm power state callback.
		*
		* @rdev: radeon_device pointer
		*
		* Look up the optimal power state based on the
		* current state of the GPU (r1xx-r5xx).
		* Used for dynpm only.
		*/
		void r100_pm_get_dynpm_state(struct radeon_device *rdev)
		{
		int i;
		@@ -223,6 +272,15 @@ void r100_pm_get_dynpm_state(struct radeon_device *rdev)
		pcie_lanes);
		}

		/**
		* r100_pm_init_profile - Initialize power profiles callback.
		*
		* @rdev: radeon_device pointer
		*
		* Initialize the power states used in profile mode
		* (r1xx-r3xx).
		* Used for profile mode only.
		*/
		void r100_pm_init_profile(struct radeon_device *rdev)
		{
		/* default */
		@@ -262,6 +320,14 @@ void r100_pm_init_profile(struct radeon_device *rdev)
		rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
		}

		/**
		* r100_pm_misc - set additional pm hw parameters callback.
		*
		* @rdev: radeon_device pointer
		*
		* Set non-clock parameters associated with a power state
		* (voltage, pcie lanes, etc.) (r1xx-r4xx).
		*/
		void r100_pm_misc(struct radeon_device *rdev)
		{
		int requested_index = rdev->pm.requested_power_state_index;
		@@ -353,6 +419,13 @@ void r100_pm_misc(struct radeon_device *rdev)
		}
		}

		/**
		* r100_pm_prepare - pre-power state change callback.
		*
		* @rdev: radeon_device pointer
		*
		* Prepare for a power state change (r1xx-r4xx).
		*/
		void r100_pm_prepare(struct radeon_device *rdev)
		{
		struct drm_device *ddev = rdev->ddev;
		@@ -377,6 +450,13 @@ void r100_pm_prepare(struct radeon_device *rdev)
		}
		}

		/**
		* r100_pm_finish - post-power state change callback.
		*
		* @rdev: radeon_device pointer
		*
		* Clean up after a power state change (r1xx-r4xx).
		*/
		void r100_pm_finish(struct radeon_device *rdev)
		{
		struct drm_device *ddev = rdev->ddev;
		@@ -401,6 +481,14 @@ void r100_pm_finish(struct radeon_device *rdev)
		}
		}

		/**
		* r100_gui_idle - gui idle callback.
		*
		* @rdev: radeon_device pointer
		*
		* Check of the GUI (2D/3D engines) are idle (r1xx-r5xx).
		* Returns true if idle, false if not.
		*/
		bool r100_gui_idle(struct radeon_device *rdev)
		{
		if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
		@@ -410,6 +498,15 @@ bool r100_gui_idle(struct radeon_device *rdev)
		}

		/* hpd for digital panel detect/disconnect */
		/**
		* r100_hpd_sense - hpd sense callback.
		*
		* @rdev: radeon_device pointer
		* @hpd: hpd (hotplug detect) pin
		*
		* Checks if a digital monitor is connected (r1xx-r4xx).
		* Returns true if connected, false if not connected.
		*/
		bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
		{
		bool connected = false;
		@@ -429,6 +526,14 @@ bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
		return connected;
		}

		/**
		* r100_hpd_set_polarity - hpd set polarity callback.
		*
		* @rdev: radeon_device pointer
		* @hpd: hpd (hotplug detect) pin
		*
		* Set the polarity of the hpd pin (r1xx-r4xx).
		*/
		void r100_hpd_set_polarity(struct radeon_device *rdev,
		enum radeon_hpd_id hpd)
		{
		@@ -457,6 +562,14 @@ void r100_hpd_set_polarity(struct radeon_device *rdev,
		}
		}

		/**
		* r100_hpd_init - hpd setup callback.
		*
		* @rdev: radeon_device pointer
		*
		* Setup the hpd pins used by the card (r1xx-r4xx).
		* Set the polarity, and enable the hpd interrupts.
		*/
		void r100_hpd_init(struct radeon_device *rdev)
		{
		struct drm_device *dev = rdev->ddev;
		@@ -471,6 +584,14 @@ void r100_hpd_init(struct radeon_device *rdev)
		radeon_irq_kms_enable_hpd(rdev, enable);
		}

		/**
		* r100_hpd_fini - hpd tear down callback.
		*
		* @rdev: radeon_device pointer
		*
		* Tear down the hpd pins used by the card (r1xx-r4xx).
		* Disable the hpd interrupts.
		*/
		void r100_hpd_fini(struct radeon_device *rdev)
		{
		struct drm_device *dev = rdev->ddev;
		@@ -1060,6 +1181,14 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
		}
		ring->ready = true;
		radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);

		if (radeon_ring_supports_scratch_reg(rdev, ring)) {
		r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
		if (r) {
		DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
		ring->rptr_save_reg = 0;
		}
		}
		return 0;
		}

		@@ -1070,6 +1199,7 @@ void r100_cp_fini(struct radeon_device *rdev)
		}
		/* Disable ring */
		r100_cp_disable(rdev);
		radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg);
		radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
		DRM_INFO("radeon: cp finalized\n");
		}
		@@ -3661,6 +3791,12 @@ void r100_ring_ib_execute(struct radeon_device rdev, struct radeon_ib ib)
		{
		struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];

		if (ring->rptr_save_reg) {
		u32 next_rptr = ring->wptr + 2 + 3;
		radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0));
		radeon_ring_write(ring, next_rptr);
		}

		radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
		radeon_ring_write(ring, ib->gpu_addr);
		radeon_ring_write(ring, ib->length_dw);
		@@ -3693,7 +3829,7 @@ int r100_ib_test(struct radeon_device rdev, struct radeon_ring ring)
		ib.ptr[6] = PACKET2(0);
		ib.ptr[7] = PACKET2(0);
		ib.length_dw = 8;
		r = radeon_ib_schedule(rdev, &ib);
		r = radeon_ib_schedule(rdev, &ib, NULL);
		if (r) {
		radeon_scratch_free(rdev, scratch);
		radeon_ib_free(rdev, &ib);

drivers/gpu/drm/radeon/r600.c

+21 −12

Original line number	Diff line number	Diff line
		@@ -2163,12 +2163,14 @@ void r600_ring_init(struct radeon_device rdev, struct radeon_ring ring, unsign
		ring->ring_size = ring_size;
		ring->align_mask = 16 - 1;

		if (radeon_ring_supports_scratch_reg(rdev, ring)) {
		r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
		if (r) {
		DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
		ring->rptr_save_reg = 0;
		}
		}
		}

		void r600_cp_fini(struct radeon_device *rdev)
		{
		@@ -2198,7 +2200,7 @@ int r600_ring_test(struct radeon_device rdev, struct radeon_ring ring)
		{
		uint32_t scratch;
		uint32_t tmp = 0;
		unsigned i, ridx = radeon_ring_index(rdev, ring);
		unsigned i;
		int r;

		r = radeon_scratch_get(rdev, &scratch);
		@@ -2209,7 +2211,7 @@ int r600_ring_test(struct radeon_device rdev, struct radeon_ring ring)
		WREG32(scratch, 0xCAFEDEAD);
		r = radeon_ring_lock(rdev, ring, 3);
		if (r) {
		DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ridx, r);
		DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r);
		radeon_scratch_free(rdev, scratch);
		return r;
		}
		@@ -2224,10 +2226,10 @@ int r600_ring_test(struct radeon_device rdev, struct radeon_ring ring)
		DRM_UDELAY(1);
		}
		if (i < rdev->usec_timeout) {
		DRM_INFO("ring test on %d succeeded in %d usecs\n", ridx, i);
		DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
		} else {
		DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
		ridx, scratch, tmp);
		ring->idx, scratch, tmp);
		r = -EINVAL;
		}
		radeon_scratch_free(rdev, scratch);
		@@ -2576,13 +2578,21 @@ void r600_fini(struct radeon_device *rdev)
		void r600_ring_ib_execute(struct radeon_device rdev, struct radeon_ib ib)
		{
		struct radeon_ring *ring = &rdev->ring[ib->ring];
		u32 next_rptr;

		if (ring->rptr_save_reg) {
		uint32_t next_rptr = ring->wptr + 3 + 4;
		next_rptr = ring->wptr + 3 + 4;
		radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
		radeon_ring_write(ring, ((ring->rptr_save_reg -
		PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
		radeon_ring_write(ring, next_rptr);
		} else if (rdev->wb.enabled) {
		next_rptr = ring->wptr + 5 + 4;
		radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
		radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
		radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) \| (1 << 18));
		radeon_ring_write(ring, next_rptr);
		radeon_ring_write(ring, 0);
		}

		radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
		@@ -2602,7 +2612,6 @@ int r600_ib_test(struct radeon_device rdev, struct radeon_ring ring)
		uint32_t tmp = 0;
		unsigned i;
		int r;
		int ring_index = radeon_ring_index(rdev, ring);

		r = radeon_scratch_get(rdev, &scratch);
		if (r) {
		@@ -2610,7 +2619,7 @@ int r600_ib_test(struct radeon_device rdev, struct radeon_ring ring)
		return r;
		}
		WREG32(scratch, 0xCAFEDEAD);
		r = radeon_ib_get(rdev, ring_index, &ib, 256);
		r = radeon_ib_get(rdev, ring->idx, &ib, 256);
		if (r) {
		DRM_ERROR("radeon: failed to get ib (%d).\n", r);
		return r;
		@@ -2619,7 +2628,7 @@ int r600_ib_test(struct radeon_device rdev, struct radeon_ring ring)
		ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
		ib.ptr[2] = 0xDEADBEEF;
		ib.length_dw = 3;
		r = radeon_ib_schedule(rdev, &ib);
		r = radeon_ib_schedule(rdev, &ib, NULL);
		if (r) {
		radeon_scratch_free(rdev, scratch);
		radeon_ib_free(rdev, &ib);

drivers/gpu/drm/radeon/radeon.h

+9 −3

Original line number	Diff line number	Diff line
		@@ -362,7 +362,7 @@ struct radeon_bo_list {
		* alignment).
		*/
		struct radeon_sa_manager {
		spinlock_t lock;
		wait_queue_head_t wq;
		struct radeon_bo *bo;
		struct list_head *hole;
		struct list_head flist[RADEON_NUM_RINGS];
		@@ -623,6 +623,8 @@ struct radeon_ring {
		unsigned rptr_offs;
		unsigned rptr_reg;
		unsigned rptr_save_reg;
		u64 next_rptr_gpu_addr;
		volatile u32 *next_rptr_cpu_addr;
		unsigned wptr;
		unsigned wptr_old;
		unsigned wptr_reg;
		@@ -638,6 +640,7 @@ struct radeon_ring {
		u32 ptr_reg_shift;
		u32 ptr_reg_mask;
		u32 nop;
		u32 idx;
		};

		/*
		@@ -751,12 +754,14 @@ struct si_rlc {
		int radeon_ib_get(struct radeon_device *rdev, int ring,
		struct radeon_ib *ib, unsigned size);
		void radeon_ib_free(struct radeon_device rdev, struct radeon_ib ib);
		int radeon_ib_schedule(struct radeon_device rdev, struct radeon_ib ib);
		int radeon_ib_schedule(struct radeon_device rdev, struct radeon_ib ib,
		struct radeon_ib *const_ib);
		int radeon_ib_pool_init(struct radeon_device *rdev);
		void radeon_ib_pool_fini(struct radeon_device *rdev);
		int radeon_ib_ring_tests(struct radeon_device *rdev);
		/* Ring access between begin & end cannot sleep */
		int radeon_ring_index(struct radeon_device rdev, struct radeon_ring cp);
		bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
		struct radeon_ring *ring);
		void radeon_ring_free_size(struct radeon_device rdev, struct radeon_ring cp);
		int radeon_ring_alloc(struct radeon_device rdev, struct radeon_ring cp, unsigned ndw);
		int radeon_ring_lock(struct radeon_device rdev, struct radeon_ring cp, unsigned ndw);
		@@ -870,6 +875,7 @@ struct radeon_wb {
		};

		#define RADEON_WB_SCRATCH_OFFSET 0
		#define RADEON_WB_RING0_NEXT_RPTR 256
		#define RADEON_WB_CP_RPTR_OFFSET 1024
		#define RADEON_WB_CP1_RPTR_OFFSET 1280
		#define RADEON_WB_CP2_RPTR_OFFSET 1536

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