Commit b682242f authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mailbox-v5.4' of git://git.linaro.org/landing-teams/working/fujitsu/integration 

Pull mailbox updates from Jassi Brar:

 - qcom:
     - enable support for ipq8074, sm1850 and sm7180
     - add child device node for qcs404
     - misc fixes

 - mediatek:
     - enable support for mt8183
     - misc rejig of cmdq driver
     - new client-reg dt property

 - armada:
     - use device-managed registration api

* tag 'mailbox-v5.4' of git://git.linaro.org/landing-teams/working/fujitsu/integration:
  mailbox: qcom-apcs: fix max_register value
  mailbox: qcom: Add support for IPQ8074 APCS
  dt-bindings: mailbox: qom: Add ipq8074 APPS compatible
  mailbox: qcom: Add support for Qualcomm SM8150 and SC7180 SoCs
  dt-bindings: mailbox: Add APSS shared for SM8150 and SC7180 SoCs
  mbox: qcom: replace integer with valid macro
  mbox: qcom: add APCS child device for QCS404
  mailbox: mediatek: cmdq: clear the event in cmdq initial flow
  mailbox: mediatek: cmdq: support mt8183 gce function
  mailbox: mediatek: cmdq: move the CMDQ_IRQ_MASK into cmdq driver data
  dt-binding: gce: add binding for gce client reg property
  dt-binding: gce: add gce header file for mt8183
  dt-binding: gce: remove thread-num property
  mailbox: armada-37xx-rwtm: Use device-managed registration API
parents e3a008ac 556a0964

Documentation/devicetree/bindings/mailbox/mtk-gce.txt

+15 −8
Original line number Diff line number Diff line
@@ -9,7 +9,7 @@ CMDQ driver uses mailbox framework for communication. Please refer to 
mailbox.txt for generic information about mailbox device-tree bindings.



Required properties:

- compatible: Must be "mediatek,mt8173-gce"

- compatible: can be "mediatek,mt8173-gce" or "mediatek,mt8183-gce"

- reg: Address range of the GCE unit

- interrupts: The interrupt signal from the GCE block

- clock: Clocks according to the common clock binding
@@ -25,11 +25,19 @@ Required properties: 
Required properties for a client device:

- mboxes: Client use mailbox to communicate with GCE, it should have this

  property and list of phandle, mailbox specifiers.

- mediatek,gce-subsys: u32, specify the sub-system id which is corresponding

Optional properties for a client device:

- mediatek,gce-client-reg: Specify the sub-system id which is corresponding

  to the register address, it should have this property and list of phandle,

  sub-system specifiers.

  <&phandle subsys_number start_offset size>

  phandle: Label name of a gce node.

  subsys_number: specify the sub-system id which is corresponding

                 to the register address.

  start_offset: the start offset of register address that GCE can access.

  size: the total size of register address that GCE can access.



Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h'. Such as

sub-system ids, thread priority, event ids.

Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h'

or 'dt-binding/gce/mt8183-gce.h'. Such as sub-system ids, thread priority, event ids.



Example:
@@ -39,7 +47,6 @@ Example: 
		interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&infracfg CLK_INFRA_GCE>;

		clock-names = "gce";

		thread-num = CMDQ_THR_MAX_COUNT;

		#mbox-cells = <3>;

	};
@@ -49,9 +56,9 @@ Example for a client device: 
		compatible = "mediatek,mt8173-mmsys";

		mboxes = <&gce 0 CMDQ_THR_PRIO_LOWEST 1>,

			 <&gce 1 CMDQ_THR_PRIO_LOWEST 1>;

		mediatek,gce-subsys = <SUBSYS_1400XXXX>;

		mutex-event-eof = <CMDQ_EVENT_MUTEX0_STREAM_EOF

				CMDQ_EVENT_MUTEX1_STREAM_EOF>;



		mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>,

					  <&gce SUBSYS_1401XXXX 0x2000 0x100>;

		...

	};

Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt

+3 −0
Original line number Diff line number Diff line
@@ -12,7 +12,10 @@ platforms. 
		    "qcom,msm8996-apcs-hmss-global"

		    "qcom,msm8998-apcs-hmss-global"

		    "qcom,qcs404-apcs-apps-global"

		    "qcom,sc7180-apss-shared"

		    "qcom,sdm845-apss-shared"

		    "qcom,sm8150-apss-shared"

		    "qcom,ipq8074-apcs-apps-global"



- reg:

	Usage: required

drivers/mailbox/armada-37xx-rwtm-mailbox.c

+1 −13
Original line number Diff line number Diff line
@@ -180,7 +180,7 @@ static int armada_37xx_mbox_probe(struct platform_device *pdev) 
	mbox->controller.ops = &a37xx_mbox_ops;

	mbox->controller.txdone_irq = true;



	ret = mbox_controller_register(&mbox->controller);

	ret = devm_mbox_controller_register(mbox->dev, &mbox->controller);

	if (ret) {

		dev_err(&pdev->dev, "Could not register mailbox controller\n");

		return ret;
@@ -190,17 +190,6 @@ static int armada_37xx_mbox_probe(struct platform_device *pdev) 
	return ret;

}



static int armada_37xx_mbox_remove(struct platform_device *pdev)

{

	struct a37xx_mbox *mbox = platform_get_drvdata(pdev);



	if (!mbox)

		return -EINVAL;



	mbox_controller_unregister(&mbox->controller);



	return 0;

}



static const struct of_device_id armada_37xx_mbox_match[] = {

	{ .compatible = "marvell,armada-3700-rwtm-mailbox" },
@@ -211,7 +200,6 @@ MODULE_DEVICE_TABLE(of, armada_37xx_mbox_match); 


static struct platform_driver armada_37xx_mbox_driver = {

	.probe	= armada_37xx_mbox_probe,

	.remove	= armada_37xx_mbox_remove,

	.driver	= {

		.name		= DRIVER_NAME,

		.of_match_table	= armada_37xx_mbox_match,

drivers/mailbox/mtk-cmdq-mailbox.c

+13 −5
Original line number Diff line number Diff line
@@ -18,10 +18,10 @@ 
#include <linux/of_device.h>



#define CMDQ_OP_CODE_MASK		(0xff << CMDQ_OP_CODE_SHIFT)

#define CMDQ_IRQ_MASK			0xffff

#define CMDQ_NUM_CMD(t)			(t->cmd_buf_size / CMDQ_INST_SIZE)



#define CMDQ_CURR_IRQ_STATUS		0x10

#define CMDQ_SYNC_TOKEN_UPDATE		0x68

#define CMDQ_THR_SLOT_CYCLES		0x30

#define CMDQ_THR_BASE			0x100

#define CMDQ_THR_SIZE			0x80
@@ -72,6 +72,7 @@ struct cmdq { 
	void __iomem		*base;

	u32			irq;

	u32			thread_nr;

	u32			irq_mask;

	struct cmdq_thread	*thread;

	struct clk		*clock;

	bool			suspended;
@@ -104,8 +105,12 @@ static void cmdq_thread_resume(struct cmdq_thread *thread) 


static void cmdq_init(struct cmdq *cmdq)

{

	int i;



	WARN_ON(clk_enable(cmdq->clock) < 0);

	writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES);

	for (i = 0; i <= CMDQ_MAX_EVENT; i++)

		writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE);

	clk_disable(cmdq->clock);

}
@@ -285,11 +290,11 @@ static irqreturn_t cmdq_irq_handler(int irq, void *dev) 
	unsigned long irq_status, flags = 0L;

	int bit;



	irq_status = readl(cmdq->base + CMDQ_CURR_IRQ_STATUS) & CMDQ_IRQ_MASK;

	if (!(irq_status ^ CMDQ_IRQ_MASK))

	irq_status = readl(cmdq->base + CMDQ_CURR_IRQ_STATUS) & cmdq->irq_mask;

	if (!(irq_status ^ cmdq->irq_mask))

		return IRQ_NONE;



	for_each_clear_bit(bit, &irq_status, fls(CMDQ_IRQ_MASK)) {

	for_each_clear_bit(bit, &irq_status, cmdq->thread_nr) {

		struct cmdq_thread *thread = &cmdq->thread[bit];



		spin_lock_irqsave(&thread->chan->lock, flags);
@@ -473,6 +478,9 @@ static int cmdq_probe(struct platform_device *pdev) 
		dev_err(dev, "failed to get irq\n");

		return -EINVAL;

	}



	cmdq->thread_nr = (u32)(unsigned long)of_device_get_match_data(dev);

	cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);

	err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,

			       "mtk_cmdq", cmdq);

	if (err < 0) {
@@ -489,7 +497,6 @@ static int cmdq_probe(struct platform_device *pdev) 
		return PTR_ERR(cmdq->clock);

	}



	cmdq->thread_nr = (u32)(unsigned long)of_device_get_match_data(dev);

	cmdq->mbox.dev = dev;

	cmdq->mbox.chans = devm_kcalloc(dev, cmdq->thread_nr,

					sizeof(*cmdq->mbox.chans), GFP_KERNEL);
@@ -537,6 +544,7 @@ static const struct dev_pm_ops cmdq_pm_ops = { 


static const struct of_device_id cmdq_of_ids[] = {

	{.compatible = "mediatek,mt8173-gce", .data = (void *)16},

	{.compatible = "mediatek,mt8183-gce", .data = (void *)24},

	{}

};

drivers/mailbox/qcom-apcs-ipc-mailbox.c

+12 −4
Original line number Diff line number Diff line
@@ -28,7 +28,7 @@ static const struct regmap_config apcs_regmap_config = { 
	.reg_bits = 32,

	.reg_stride = 4,

	.val_bits = 32,

	.max_register = 0x1000,

	.max_register = 0xFFC,

	.fast_io = true,

};
@@ -47,7 +47,6 @@ static const struct mbox_chan_ops qcom_apcs_ipc_ops = { 


static int qcom_apcs_ipc_probe(struct platform_device *pdev)

{

	struct device_node *np = pdev->dev.of_node;

	struct qcom_apcs_ipc *apcs;

	struct regmap *regmap;

	struct resource *res;
@@ -55,6 +54,11 @@ static int qcom_apcs_ipc_probe(struct platform_device *pdev) 
	void __iomem *base;

	unsigned long i;

	int ret;

	const struct of_device_id apcs_clk_match_table[] = {

		{ .compatible = "qcom,msm8916-apcs-kpss-global", },

		{ .compatible = "qcom,qcs404-apcs-apps-global", },

		{}

	};



	apcs = devm_kzalloc(&pdev->dev, sizeof(*apcs), GFP_KERNEL);

	if (!apcs)
@@ -89,10 +93,11 @@ static int qcom_apcs_ipc_probe(struct platform_device *pdev) 
		return ret;

	}



	if (of_device_is_compatible(np, "qcom,msm8916-apcs-kpss-global")) {

	if (of_match_device(apcs_clk_match_table, &pdev->dev)) {

		apcs->clk = platform_device_register_data(&pdev->dev,

							  "qcom-apcs-msm8916-clk",

							  -1, NULL, 0);

							  PLATFORM_DEVID_NONE,

							  NULL, 0);

		if (IS_ERR(apcs->clk))

			dev_err(&pdev->dev, "failed to register APCS clk\n");

	}
@@ -118,7 +123,10 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = { 
	{ .compatible = "qcom,msm8996-apcs-hmss-global", .data = (void *)16 },

	{ .compatible = "qcom,msm8998-apcs-hmss-global", .data = (void *)8 },

	{ .compatible = "qcom,qcs404-apcs-apps-global", .data = (void *)8 },

	{ .compatible = "qcom,sc7180-apss-shared", .data = (void *)12 },

	{ .compatible = "qcom,sdm845-apss-shared", .data = (void *)12 },

	{ .compatible = "qcom,sm8150-apss-shared", .data = (void *)12 },

	{ .compatible = "qcom,ipq8074-apcs-apps-global", .data = (void *)8 },

	{}

};

MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match);

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