Merge tag 'lpc32xx-soc-4.7' of git://github.com/vzapolskiy/linux-lpc32xx into next/soc (b65b98d9) · Commits · 戴 / test

arch/arm/mach-lpc32xx/common.c

+0 −95

Original line number	Diff line number	Diff line
		@@ -17,13 +17,6 @@
		*/

		#include <linux/init.h>
		#include <linux/platform_device.h>
		#include <linux/interrupt.h>
		#include <linux/irq.h>
		#include <linux/err.h>
		#include <linux/i2c.h>
		#include <linux/i2c-pnx.h>
		#include <linux/io.h>

		#include <asm/mach/map.h>
		#include <asm/system_info.h>
		@@ -43,19 +36,6 @@ void lpc32xx_get_uid(u32 devid[4])
		devid[i] = __raw_readl(LPC32XX_CLKPWR_DEVID(i << 2));
		}

		/*
		* Returns SYSCLK source
		* 0 = PLL397, 1 = main oscillator
		*/
		int clk_is_sysclk_mainosc(void)
		{
		if ((__raw_readl(LPC32XX_CLKPWR_SYSCLK_CTRL) &
		LPC32XX_CLKPWR_SYSCTRL_SYSCLKMUX) == 0)
		return 1;

		return 0;
		}

		/*
		* Detects and returns IRAM size for the device variation
		*/
		@@ -87,81 +67,6 @@ u32 lpc32xx_return_iram_size(void)
		}
		EXPORT_SYMBOL_GPL(lpc32xx_return_iram_size);

		/*
		* Computes PLL rate from PLL register and input clock
		*/
		u32 clk_check_pll_setup(u32 ifreq, struct clk_pll_setup *pllsetup)
		{
		u32 ilfreq, p, m, n, fcco, fref, cfreq;
		int mode;

		/*
		* PLL requirements
		* ifreq must be >= 1MHz and <= 20MHz
		* FCCO must be >= 156MHz and <= 320MHz
		* FREF must be >= 1MHz and <= 27MHz
		* Assume the passed input data is not valid
		*/

		ilfreq = ifreq;
		m = pllsetup->pll_m;
		n = pllsetup->pll_n;
		p = pllsetup->pll_p;

		mode = (pllsetup->cco_bypass_b15 << 2) \|
		(pllsetup->direct_output_b14 << 1) \|
		pllsetup->fdbk_div_ctrl_b13;

		switch (mode) {
		case 0x0: /* Non-integer mode */
		cfreq = (m * ilfreq) / (2 * p * n);
		fcco = (m * ilfreq) / n;
		fref = ilfreq / n;
		break;

		case 0x1: /* integer mode */
		cfreq = (m * ilfreq) / n;
		fcco = (m * ilfreq) / (n * 2 * p);
		fref = ilfreq / n;
		break;

		case 0x2:
		case 0x3: /* Direct mode */
		cfreq = (m * ilfreq) / n;
		fcco = cfreq;
		fref = ilfreq / n;
		break;

		case 0x4:
		case 0x5: /* Bypass mode */
		cfreq = ilfreq / (2 * p);
		fcco = 156000000;
		fref = 1000000;
		break;

		case 0x6:
		case 0x7: /* Direct bypass mode */
		default:
		cfreq = ilfreq;
		fcco = 156000000;
		fref = 1000000;
		break;
		}

		if (fcco < 156000000 \|\| fcco > 320000000)
		cfreq = 0;

		if (fref < 1000000 \|\| fref > 27000000)
		cfreq = 0;

		return (u32) cfreq;
		}

		u32 clk_get_pclk_div(void)
		{
		return 1 + ((__raw_readl(LPC32XX_CLKPWR_HCLK_DIV) >> 2) & 0x1F);
		}

		static struct map_desc lpc32xx_io_desc[] __initdata = {
		{
		.virtual = (unsigned long)IO_ADDRESS(LPC32XX_AHB0_START),

arch/arm/mach-lpc32xx/common.h

+1 −23

Original line number	Diff line number	Diff line
		@@ -19,37 +19,15 @@
		#ifndef __LPC32XX_COMMON_H
		#define __LPC32XX_COMMON_H

		#include <mach/board.h>
		#include <linux/platform_device.h>
		#include <linux/reboot.h>
		#include <linux/init.h>

		/*
		* Other arch specific structures and functions
		*/
		extern void lpc32xx_timer_init(void);
		extern void __init lpc32xx_init_irq(void);
		extern void __init lpc32xx_map_io(void);
		extern void __init lpc32xx_serial_init(void);


		/*
		* Structure used for setting up and querying the PLLS
		*/
		struct clk_pll_setup {
		int analog_on;
		int cco_bypass_b15;
		int direct_output_b14;
		int fdbk_div_ctrl_b13;
		int pll_p;
		int pll_n;
		u32 pll_m;
		};

		extern int clk_is_sysclk_mainosc(void);
		extern u32 clk_check_pll_setup(u32 ifreq, struct clk_pll_setup *pllsetup);
		extern u32 clk_get_pllrate_from_reg(u32 inputclk, u32 regval);
		extern u32 clk_get_pclk_div(void);

		/*
		* Returns the LPC32xx unique 128-bit chip ID
		*/

arch/arm/mach-lpc32xx/phy3250.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -159,7 +159,7 @@ static struct lpc32xx_mlc_platform_data lpc32xx_mlc_data = {
		.dma_filter = pl08x_filter_id,
		};

		static const struct of_dev_auxdata const lpc32xx_auxdata_lookup[] __initconst = {
		static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
		OF_DEV_AUXDATA("arm,pl022", 0x20084000, "dev:ssp0", NULL),
		OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", NULL),
		OF_DEV_AUXDATA("arm,pl110", 0x31040000, "dev:clcd", &lpc32xx_clcd_data),

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