Commit b633648c authored by Ralf Baechle's avatar Ralf Baechle
Browse files

MIPS: MT: Remove SMTC support 

Nobody is maintaining SMTC anymore and there also seems to be no userbase.
Which is a pity - the SMTC technology primarily developed by Kevin D.
Kissell <kevink@paralogos.com> is an ingenious demonstration for the MT
ASE's power and elegance.

Based on Markos Chandras <Markos.Chandras@imgtec.com> patch
https://patchwork.linux-mips.org/patch/6719/

 which while very similar did
no longer apply cleanly when I tried to merge it plus some additional
post-SMTC cleanup - SMTC was a feature as tricky to remove as it was to
merge once upon a time.

Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 8b2e62cc

arch/mips/Kconfig

+4 −45
Original line number Diff line number Diff line
@@ -1852,7 +1852,7 @@ config FORCE_MAX_ZONEORDER 


config CEVT_GIC

	bool "Use GIC global counter for clock events"

	depends on IRQ_GIC && !(MIPS_SEAD3 || MIPS_MT_SMTC)

	depends on IRQ_GIC && !MIPS_SEAD3

	help

	  Use the GIC global counter for the clock events. The R4K clock

	  event driver is always present, so if the platform ends up not
@@ -1936,24 +1936,6 @@ config MIPS_MT_SMP 
	  Intel Hyperthreading feature. For further information go to

	  <http://www.imgtec.com/mips/mips-multithreading.asp>.



config MIPS_MT_SMTC

	bool "Use all TCs on all VPEs for SMP (DEPRECATED)"

	depends on CPU_MIPS32_R2

	depends on SYS_SUPPORTS_MULTITHREADING

	depends on !MIPS_CPS

	select CPU_MIPSR2_IRQ_VI

	select CPU_MIPSR2_IRQ_EI

	select MIPS_MT

	select SMP

	select SMP_UP

	select SYS_SUPPORTS_SMP

	select NR_CPUS_DEFAULT_8

	help

	  This is a kernel model which is known as SMTC. This is

	  supported on cores with the MT ASE and presents all TCs

	  available on all VPEs to support SMP. For further

	  information see <http://www.linux-mips.org/wiki/34K#SMTC>.



endchoice



config MIPS_MT
@@ -1977,7 +1959,7 @@ config SYS_SUPPORTS_MULTITHREADING 
config MIPS_MT_FPAFF

	bool "Dynamic FPU affinity for FP-intensive threads"

	default y

	depends on MIPS_MT_SMP || MIPS_MT_SMTC

	depends on MIPS_MT_SMP



config MIPS_VPE_LOADER

	bool "VPE loader support."
@@ -1999,29 +1981,6 @@ config MIPS_VPE_LOADER_MT 
	default "y"

	depends on MIPS_VPE_LOADER && !MIPS_CMP



config MIPS_MT_SMTC_IM_BACKSTOP

	bool "Use per-TC register bits as backstop for inhibited IM bits"

	depends on MIPS_MT_SMTC

	default n

	help

	  To support multiple TC microthreads acting as "CPUs" within

	  a VPE, VPE-wide interrupt mask bits must be specially manipulated

	  during interrupt handling. To support legacy drivers and interrupt

	  controller management code, SMTC has a "backstop" to track and

	  if necessary restore the interrupt mask. This has some performance

	  impact on interrupt service overhead.



config MIPS_MT_SMTC_IRQAFF

	bool "Support IRQ affinity API"

	depends on MIPS_MT_SMTC

	default n

	help

	  Enables SMP IRQ affinity API (/proc/irq/*/smp_affinity, etc.)

	  for SMTC Linux kernel. Requires platform support, of which

	  an example can be found in the MIPS kernel i8259 and Malta

	  platform code.  Adds some overhead to interrupt dispatch, and

	  should be used only if you know what you are doing.



config MIPS_VPE_LOADER_TOM

	bool "Load VPE program into memory hidden from linux"

	depends on MIPS_VPE_LOADER
@@ -2049,7 +2008,7 @@ config MIPS_VPE_APSP_API_MT 


config MIPS_CMP

	bool "MIPS CMP framework support (DEPRECATED)"

	depends on SYS_SUPPORTS_MIPS_CMP && !MIPS_MT_SMTC

	depends on SYS_SUPPORTS_MIPS_CMP

	select MIPS_GIC_IPI

	select SYNC_R4K

	select WEAK_ORDERING
@@ -2256,7 +2215,7 @@ config NODES_SHIFT 


config HW_PERF_EVENTS

	bool "Enable hardware performance counter support for perf events"

	depends on PERF_EVENTS && !MIPS_MT_SMTC && OPROFILE=n && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP)

	depends on PERF_EVENTS && OPROFILE=n && (CPU_MIPS32 || CPU_MIPS64 || CPU_R10000 || CPU_SB1 || CPU_CAVIUM_OCTEON || CPU_XLP)

	default y

	help

	  Enable hardware performance counter support for perf events. If

arch/mips/Kconfig.debug

+0 −9
Original line number Diff line number Diff line
@@ -79,15 +79,6 @@ config CMDLINE_OVERRIDE 


	  Normally, you will choose 'N' here.



config SMTC_IDLE_HOOK_DEBUG

	bool "Enable additional debug checks before going into CPU idle loop"

	depends on DEBUG_KERNEL && MIPS_MT_SMTC

	help

	  This option enables Enable additional debug checks before going into

	  CPU idle loop.  For details on these checks, see

	  arch/mips/kernel/smtc.c.  This debugging option result in significant

	  overhead so should be disabled in production kernels.



config SB1XXX_CORELIS

	bool "Corelis Debugger"

	depends on SIBYTE_SB1xxx_SOC

arch/mips/configs/maltasmtc_defconfig

deleted100644 → 0
+0 −196
Original line number Diff line number Diff line 
CONFIG_MIPS_MALTA=y

CONFIG_CPU_LITTLE_ENDIAN=y

CONFIG_CPU_MIPS32_R2=y

CONFIG_PAGE_SIZE_16KB=y

CONFIG_MIPS_MT_SMTC=y

# CONFIG_MIPS_MT_FPAFF is not set

CONFIG_NR_CPUS=9

CONFIG_HZ_48=y

CONFIG_LOCALVERSION="smtc"

CONFIG_SYSVIPC=y

CONFIG_POSIX_MQUEUE=y

CONFIG_AUDIT=y

CONFIG_IKCONFIG=y

CONFIG_IKCONFIG_PROC=y

CONFIG_LOG_BUF_SHIFT=15

CONFIG_SYSCTL_SYSCALL=y

CONFIG_EMBEDDED=y

CONFIG_SLAB=y

CONFIG_MODULES=y

CONFIG_MODULE_UNLOAD=y

CONFIG_MODVERSIONS=y

CONFIG_MODULE_SRCVERSION_ALL=y

# CONFIG_BLK_DEV_BSG is not set

CONFIG_PCI=y

# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set

CONFIG_NET=y

CONFIG_PACKET=y

CONFIG_UNIX=y

CONFIG_XFRM_USER=m

CONFIG_NET_KEY=y

CONFIG_INET=y

CONFIG_IP_MULTICAST=y

CONFIG_IP_ADVANCED_ROUTER=y

CONFIG_IP_MULTIPLE_TABLES=y

CONFIG_IP_ROUTE_MULTIPATH=y

CONFIG_IP_ROUTE_VERBOSE=y

CONFIG_IP_PNP=y

CONFIG_IP_PNP_DHCP=y

CONFIG_IP_PNP_BOOTP=y

CONFIG_NET_IPIP=m

CONFIG_IP_MROUTE=y

CONFIG_IP_PIMSM_V1=y

CONFIG_IP_PIMSM_V2=y

CONFIG_SYN_COOKIES=y

CONFIG_INET_AH=m

CONFIG_INET_ESP=m

CONFIG_INET_IPCOMP=m

# CONFIG_INET_LRO is not set

CONFIG_INET6_AH=m

CONFIG_INET6_ESP=m

CONFIG_INET6_IPCOMP=m

CONFIG_IPV6_TUNNEL=m

CONFIG_BRIDGE=m

CONFIG_VLAN_8021Q=m

CONFIG_ATALK=m

CONFIG_DEV_APPLETALK=m

CONFIG_IPDDP=m

CONFIG_IPDDP_ENCAP=y

CONFIG_NET_SCHED=y

CONFIG_NET_SCH_CBQ=m

CONFIG_NET_SCH_HTB=m

CONFIG_NET_SCH_HFSC=m

CONFIG_NET_SCH_PRIO=m

CONFIG_NET_SCH_RED=m

CONFIG_NET_SCH_SFQ=m

CONFIG_NET_SCH_TEQL=m

CONFIG_NET_SCH_TBF=m

CONFIG_NET_SCH_GRED=m

CONFIG_NET_SCH_DSMARK=m

CONFIG_NET_SCH_NETEM=m

CONFIG_NET_SCH_INGRESS=m

CONFIG_NET_CLS_BASIC=m

CONFIG_NET_CLS_TCINDEX=m

CONFIG_NET_CLS_ROUTE4=m

CONFIG_NET_CLS_FW=m

CONFIG_NET_CLS_U32=m

CONFIG_NET_CLS_RSVP=m

CONFIG_NET_CLS_RSVP6=m

CONFIG_NET_CLS_ACT=y

CONFIG_NET_ACT_POLICE=y

CONFIG_NET_CLS_IND=y

# CONFIG_WIRELESS is not set

CONFIG_DEVTMPFS=y

CONFIG_BLK_DEV_LOOP=y

CONFIG_BLK_DEV_CRYPTOLOOP=m

CONFIG_IDE=y

# CONFIG_IDE_PROC_FS is not set

# CONFIG_IDEPCI_PCIBUS_ORDER is not set

CONFIG_BLK_DEV_GENERIC=y

CONFIG_BLK_DEV_PIIX=y

CONFIG_SCSI=y

CONFIG_BLK_DEV_SD=y

CONFIG_CHR_DEV_SG=y

# CONFIG_SCSI_LOWLEVEL is not set

CONFIG_NETDEVICES=y

# CONFIG_NET_VENDOR_3COM is not set

# CONFIG_NET_VENDOR_ADAPTEC is not set

# CONFIG_NET_VENDOR_ALTEON is not set

CONFIG_PCNET32=y

# CONFIG_NET_VENDOR_ATHEROS is not set

# CONFIG_NET_VENDOR_BROADCOM is not set

# CONFIG_NET_VENDOR_BROCADE is not set

# CONFIG_NET_VENDOR_CHELSIO is not set

# CONFIG_NET_VENDOR_CISCO is not set

# CONFIG_NET_VENDOR_DEC is not set

# CONFIG_NET_VENDOR_DLINK is not set

# CONFIG_NET_VENDOR_EMULEX is not set

# CONFIG_NET_VENDOR_EXAR is not set

# CONFIG_NET_VENDOR_HP is not set

# CONFIG_NET_VENDOR_INTEL is not set

# CONFIG_NET_VENDOR_MARVELL is not set

# CONFIG_NET_VENDOR_MELLANOX is not set

# CONFIG_NET_VENDOR_MICREL is not set

# CONFIG_NET_VENDOR_MYRI is not set

# CONFIG_NET_VENDOR_NATSEMI is not set

# CONFIG_NET_VENDOR_NVIDIA is not set

# CONFIG_NET_VENDOR_OKI is not set

# CONFIG_NET_PACKET_ENGINE is not set

# CONFIG_NET_VENDOR_QLOGIC is not set

# CONFIG_NET_VENDOR_REALTEK is not set

# CONFIG_NET_VENDOR_RDC is not set

# CONFIG_NET_VENDOR_SEEQ is not set

# CONFIG_NET_VENDOR_SILAN is not set

# CONFIG_NET_VENDOR_SIS is not set

# CONFIG_NET_VENDOR_SMSC is not set

# CONFIG_NET_VENDOR_STMICRO is not set

# CONFIG_NET_VENDOR_SUN is not set

# CONFIG_NET_VENDOR_TEHUTI is not set

# CONFIG_NET_VENDOR_TI is not set

# CONFIG_NET_VENDOR_TOSHIBA is not set

# CONFIG_NET_VENDOR_VIA is not set

# CONFIG_WLAN is not set

# CONFIG_VT is not set

CONFIG_LEGACY_PTY_COUNT=16

CONFIG_SERIAL_8250=y

CONFIG_SERIAL_8250_CONSOLE=y

CONFIG_HW_RANDOM=y

# CONFIG_HWMON is not set

CONFIG_VIDEO_OUTPUT_CONTROL=m

CONFIG_FB=y

CONFIG_FIRMWARE_EDID=y

CONFIG_FB_MATROX=y

CONFIG_FB_MATROX_G=y

CONFIG_USB=y

CONFIG_USB_EHCI_HCD=y

# CONFIG_USB_EHCI_TT_NEWSCHED is not set

CONFIG_USB_UHCI_HCD=y

CONFIG_USB_STORAGE=y

CONFIG_NEW_LEDS=y

CONFIG_LEDS_CLASS=y

CONFIG_LEDS_TRIGGERS=y

CONFIG_LEDS_TRIGGER_TIMER=y

CONFIG_LEDS_TRIGGER_IDE_DISK=y

CONFIG_LEDS_TRIGGER_HEARTBEAT=y

CONFIG_LEDS_TRIGGER_BACKLIGHT=y

CONFIG_LEDS_TRIGGER_DEFAULT_ON=y

CONFIG_RTC_CLASS=y

CONFIG_RTC_DRV_CMOS=y

CONFIG_EXT2_FS=y

CONFIG_EXT3_FS=y

# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set

CONFIG_XFS_FS=y

CONFIG_XFS_QUOTA=y

CONFIG_XFS_POSIX_ACL=y

CONFIG_QUOTA=y

CONFIG_QFMT_V2=y

CONFIG_MSDOS_FS=m

CONFIG_VFAT_FS=m

CONFIG_PROC_KCORE=y

CONFIG_TMPFS=y

CONFIG_NFS_FS=y

CONFIG_ROOT_NFS=y

CONFIG_CIFS=m

CONFIG_CIFS_WEAK_PW_HASH=y

CONFIG_CIFS_XATTR=y

CONFIG_CIFS_POSIX=y

CONFIG_NLS_CODEPAGE_437=m

CONFIG_NLS_ISO8859_1=m

# CONFIG_FTRACE is not set

CONFIG_CRYPTO_NULL=m

CONFIG_CRYPTO_PCBC=m

CONFIG_CRYPTO_HMAC=y

CONFIG_CRYPTO_MICHAEL_MIC=m

CONFIG_CRYPTO_SHA512=m

CONFIG_CRYPTO_TGR192=m

CONFIG_CRYPTO_WP512=m

CONFIG_CRYPTO_ANUBIS=m

CONFIG_CRYPTO_BLOWFISH=m

CONFIG_CRYPTO_CAST5=m

CONFIG_CRYPTO_CAST6=m

CONFIG_CRYPTO_KHAZAD=m

CONFIG_CRYPTO_SERPENT=m

CONFIG_CRYPTO_TEA=m

CONFIG_CRYPTO_TWOFISH=m

# CONFIG_CRYPTO_ANSI_CPRNG is not set

# CONFIG_CRYPTO_HW is not set

arch/mips/include/asm/asmmacro.h

+2 −20
Original line number Diff line number Diff line
@@ -17,26 +17,8 @@ 
#ifdef CONFIG_64BIT

#include <asm/asmmacro-64.h>

#endif

#ifdef CONFIG_MIPS_MT_SMTC

#include <asm/mipsmtregs.h>

#endif



#ifdef CONFIG_MIPS_MT_SMTC

	.macro	local_irq_enable reg=t0

	mfc0	\reg, CP0_TCSTATUS

	ori	\reg, \reg, TCSTATUS_IXMT

	xori	\reg, \reg, TCSTATUS_IXMT

	mtc0	\reg, CP0_TCSTATUS

	_ehb

	.endm



	.macro	local_irq_disable reg=t0

	mfc0	\reg, CP0_TCSTATUS

	ori	\reg, \reg, TCSTATUS_IXMT

	mtc0	\reg, CP0_TCSTATUS

	_ehb

	.endm

#elif defined(CONFIG_CPU_MIPSR2)

#ifdef CONFIG_CPU_MIPSR2

	.macro	local_irq_enable reg=t0

	ei

	irq_enable_hazard
@@ -71,7 +53,7 @@ 
	sw      \reg, TI_PRE_COUNT($28)

#endif

	.endm

#endif /* CONFIG_MIPS_MT_SMTC */

#endif /* CONFIG_CPU_MIPSR2 */



	.macro	fpu_save_16even thread tmp=t0

	cfc1	\tmp, fcr31

arch/mips/include/asm/cpu-info.h

+4 −9
Original line number Diff line number Diff line
@@ -65,17 +65,12 @@ struct cpuinfo_mips { 
#ifdef CONFIG_64BIT

	int			vmbits; /* Virtual memory size in bits */

#endif

#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)

#ifdef CONFIG_MIPS_MT_SMP

	/*

	 * In the MIPS MT "SMTC" model, each TC is considered

	 * to be a "CPU" for the purposes of scheduling, but

	 * exception resources, ASID spaces, etc, are common

	 * to all TCs within the same VPE.

	 * There is not necessarily a 1:1 mapping of VPE num to CPU number

	 * in particular on multi-core systems.

	 */

	int			vpe_id;	 /* Virtual Processor number */

#endif

#ifdef CONFIG_MIPS_MT_SMTC

	int			tc_id;	 /* Thread Context number */

#endif

	void			*data;	/* Additional data */

	unsigned int		watch_reg_count;   /* Number that exist */
@@ -117,7 +112,7 @@ struct proc_cpuinfo_notifier_args { 
	unsigned long n;

};



#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)

#ifdef CONFIG_MIPS_MT_SMP

# define cpu_vpe_id(cpuinfo)	((cpuinfo)->vpe_id)

#else

# define cpu_vpe_id(cpuinfo)	0

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