Commit b632506c authored by Martin Blumenstingl's avatar Martin Blumenstingl Committed by Kevin Hilman
Browse files

ARM: dts: meson: Add the Ethernet "timing-adjustment" clock 



Add the "timing-adjusment" clock now that we now that this is connected
to the PRG_ETHERNET registers. It is used internally to generate the
RGMII RX delay no the MAC side (if needed).

Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: default avatarKevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20200512215148.540322-2-martin.blumenstingl@googlemail.com
parent f5a7382d

arch/arm/boot/dts/meson8b.dtsi

+3 −2
Original line number Diff line number Diff line
@@ -425,8 +425,9 @@ 


	clocks = <&clkc CLKID_ETH>,

		 <&clkc CLKID_MPLL2>,

		 <&clkc CLKID_MPLL2>;

	clock-names = "stmmaceth", "clkin0", "clkin1";

		 <&clkc CLKID_MPLL2>,

		 <&clkc CLKID_FCLK_DIV2>;

	clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";

	rx-fifo-depth = <4096>;

	tx-fifo-depth = <2048>;

arch/arm/boot/dts/meson8m2.dtsi

+3 −2
Original line number Diff line number Diff line
@@ -30,8 +30,9 @@ 
		0xc1108140 0x8>;

	clocks = <&clkc CLKID_ETH>,

		 <&clkc CLKID_MPLL2>,

		 <&clkc CLKID_MPLL2>;

	clock-names = "stmmaceth", "clkin0", "clkin1";

		 <&clkc CLKID_MPLL2>,

		 <&clkc CLKID_FCLK_DIV2>;

	clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";

	resets = <&reset RESET_ETHERNET>;

	reset-names = "stmmaceth";

};

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