Commit b620ba54 authored by Zhenyu Ye's avatar Zhenyu Ye Committed by Catalin Marinas
Browse files

arm64: tlb: Detect the ARMv8.4 TLBI RANGE feature 



ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
range of input addresses. This patch detect this feature.

Signed-off-by: default avatarZhenyu Ye <yezhenyu2@huawei.com>
Link: https://lore.kernel.org/r/20200715071945.897-2-yezhenyu2@huawei.com


[catalin.marinas@arm.com: some renaming for consistency]
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 61c11656

arch/arm64/include/asm/cpucaps.h

+2 −1
Original line number Diff line number Diff line
@@ -63,7 +63,8 @@ 
#define ARM64_HAS_32BIT_EL1			53

#define ARM64_BTI				54

#define ARM64_HAS_ARMv8_4_TTL			55

#define ARM64_HAS_TLB_RANGE			56



#define ARM64_NCAPS				56

#define ARM64_NCAPS				57



#endif /* __ASM_CPUCAPS_H */

arch/arm64/include/asm/sysreg.h

+3 −0
Original line number Diff line number Diff line
@@ -617,6 +617,9 @@ 
#define ID_AA64ISAR0_SHA1_SHIFT		8

#define ID_AA64ISAR0_AES_SHIFT		4



#define ID_AA64ISAR0_TLB_RANGE_NI	0x0

#define ID_AA64ISAR0_TLB_RANGE		0x2



/* id_aa64isar1 */

#define ID_AA64ISAR1_I8MM_SHIFT		52

#define ID_AA64ISAR1_DGH_SHIFT		48

arch/arm64/kernel/cpufeature.c

+10 −0
Original line number Diff line number Diff line
@@ -1893,6 +1893,16 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.min_field_value = 1,

		.matches = has_cpuid_feature,

	},

	{

		.desc = "TLB range maintenance instructions",

		.capability = ARM64_HAS_TLB_RANGE,

		.type = ARM64_CPUCAP_SYSTEM_FEATURE,

		.matches = has_cpuid_feature,

		.sys_reg = SYS_ID_AA64ISAR0_EL1,

		.field_pos = ID_AA64ISAR0_TLB_SHIFT,

		.sign = FTR_UNSIGNED,

		.min_field_value = ID_AA64ISAR0_TLB_RANGE,

	},

#ifdef CONFIG_ARM64_HW_AFDBM

	{

		/*

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