Commit b604545b authored by James Zhu's avatar James Zhu Committed by Alex Deucher
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drm/amdgpu:Add new register offset/mask to support VCN DPG mode 



New register offset/mask need to be added to support VCN DPG mode.

Signed-off-by: default avatarJames Zhu <James.Zhu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarHuang Rui <ray.huang@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 21cbe2f3

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h

+8 −0
Original line number Diff line number Diff line
@@ -33,6 +33,14 @@ 
#define mmUVD_POWER_STATUS_BASE_IDX                                                                    1

#define mmCC_UVD_HARVESTING                                                                            0x00c7

#define mmCC_UVD_HARVESTING_BASE_IDX                                                                   1

#define mmUVD_DPG_LMA_CTL                                                                              0x00d1

#define mmUVD_DPG_LMA_CTL_BASE_IDX                                                                     1

#define mmUVD_DPG_LMA_DATA                                                                             0x00d2

#define mmUVD_DPG_LMA_DATA_BASE_IDX                                                                    1

#define mmUVD_DPG_LMA_MASK                                                                             0x00d3

#define mmUVD_DPG_LMA_MASK_BASE_IDX                                                                    1

#define mmUVD_DPG_PAUSE                                                                                0x00d4

#define mmUVD_DPG_PAUSE_BASE_IDX                                                                       1

#define mmUVD_SCRATCH1                                                                                 0x00d5

#define mmUVD_SCRATCH1_BASE_IDX                                                                        1

#define mmUVD_SCRATCH2                                                                                 0x00d6

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

+25 −0
Original line number Diff line number Diff line
@@ -87,6 +87,26 @@ 
//CC_UVD_HARVESTING

#define CC_UVD_HARVESTING__UVD_DISABLE__SHIFT                                                                 0x1

#define CC_UVD_HARVESTING__UVD_DISABLE_MASK                                                                   0x00000002L

//UVD_DPG_LMA_CTL

#define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT                                                                    0x0

#define UVD_DPG_LMA_CTL__MASK_EN__SHIFT                                                                       0x1

#define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT__SHIFT                                                           0x2

#define UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT                                                                      0x4

#define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT                                                               0x10

#define UVD_DPG_LMA_CTL__READ_WRITE_MASK                                                                      0x00000001L

#define UVD_DPG_LMA_CTL__MASK_EN_MASK                                                                         0x00000002L

#define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT_MASK                                                             0x00000004L

#define UVD_DPG_LMA_CTL__SRAM_SEL_MASK                                                                        0x00000010L

#define UVD_DPG_LMA_CTL__READ_WRITE_ADDR_MASK                                                                 0xFFFF0000L

//UVD_DPG_PAUSE

#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ__SHIFT                                                              0x0

#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK__SHIFT                                                              0x1

#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ__SHIFT                                                                0x2

#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK__SHIFT                                                                0x3

#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK                                                                0x00000001L

#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK                                                                0x00000002L

#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK                                                                  0x00000004L

#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK                                                                  0x00000008L

//UVD_SCRATCH1

#define UVD_SCRATCH1__SCRATCH1_DATA__SHIFT                                                                    0x0

#define UVD_SCRATCH1__SCRATCH1_DATA_MASK                                                                      0xFFFFFFFFL
@@ -983,6 +1003,7 @@ 
#define UVD_MASTINT_EN__SYS_EN_MASK                                                                           0x00000004L

#define UVD_MASTINT_EN__INT_OVERRUN_MASK                                                                      0x007FFFF0L

//UVD_SYS_INT_EN

#define UVD_SYS_INT_EN__UVD_JRBC_EN__SHIFT                                                                    0x4

#define UVD_SYS_INT_EN__UVD_JRBC_EN_MASK                                                                      0x00000010L

//JPEG_CGC_CTRL

#define JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT                                                                  0x0
@@ -1138,7 +1159,11 @@ 
#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK                                                                0x001FFFFFL

//UVD_VCPU_CNTL

#define UVD_VCPU_CNTL__CLK_EN__SHIFT                                                                          0x9

#define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP__SHIFT                                                         0x11

#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT                                                                 0x14

#define UVD_VCPU_CNTL__CLK_EN_MASK                                                                            0x00000200L

#define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK                                                           0x00020000L

#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK                                                                   0x0FF00000L

//UVD_SOFT_RESET

#define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT                                                                 0x0

#define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT                                                                0x1

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