Commit b5fb0b1b authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge branch 'add-support-for-marvell-octeontx2-cryptographic' 

Srujana Challa says:

====================
Add Support for Marvell OcteonTX2 Cryptographic

This patchset adds support for CPT in OcteonTX2 admin function(AF).
CPT is a cryptographic accelerator unit and it includes microcoded
Giga Cipher engines.

OcteonTX2 SOC's resource virtualization unit (RVU) supports multiple
physical and virtual functions. Each of the PF/VF's functionality is
determined by what kind of resources are attached to it. When the CPT
block is attached to a VF, it can function as a security device.
The following document provides an overview of the hardware and
different drivers for the OcteonTX2 SOC:
https://www.kernel.org/doc/Documentation/networking/device_drivers/marvell/octeontx2.rst

This patch series includes:
- Patch to update existing Marvell sources to support CPT.
- Patch that adds mailbox messages to the admin function (AF) driver,
to configure CPT HW registers.
- Patch to provide debug information about CPT.
====================

Link: https://lore.kernel.org/r/20201118114416.28307-1-schalla@marvell.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents 1a0058cf 76638a2e

MAINTAINERS

+2 −0
Original line number Diff line number Diff line
@@ -10453,6 +10453,7 @@ M: Srujana Challa <schalla@marvell.com> 
L:	linux-crypto@vger.kernel.org

S:	Maintained

F:	drivers/crypto/marvell/

F:	include/linux/soc/marvell/octeontx2/















MARVELL GIGABIT ETHERNET DRIVERS (skge/sky2)















M:	Mirko Lindner <mlindner@marvell.com>










@@ -10525,6 +10526,7 @@ M:	hariprasad <hkelam@marvell.com>













L:	netdev@vger.kernel.org















S:	Supported















F:	drivers/net/ethernet/marvell/octeontx2/nic/













F:	include/linux/soc/marvell/octeontx2/





























MARVELL OCTEONTX2 RVU ADMIN FUNCTION DRIVER















M:	Sunil Goutham <sgoutham@marvell.com>

































drivers/net/ethernet/marvell/octeontx2/af/Makefile



+2
−1






























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@@ -9,4 +9,5 @@ obj-$(CONFIG_OCTEONTX2_AF) += octeontx2_af.o





























octeontx2_mbox-y := mbox.o rvu_trace.o















octeontx2_af-y := cgx.o rvu.o rvu_cgx.o rvu_npa.o rvu_nix.o \













		  rvu_reg.o rvu_npc.o rvu_debugfs.o ptp.o rvu_npc_fs.o












		  rvu_reg.o rvu_npc.o rvu_debugfs.o ptp.o rvu_npc_fs.o \













		  rvu_cpt.o
























drivers/net/ethernet/marvell/octeontx2/af/mbox.h



+33
−0






























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@@ -158,6 +158,11 @@ M(NPA_HWCTX_DISABLE,	0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\













/* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */				\















/* TIM mbox IDs (range 0x800 - 0x9FF) */				\















/* CPT mbox IDs (range 0xA00 - 0xBFF) */				\













M(CPT_LF_ALLOC,		0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg,	\













			       msg_rsp)					\













M(CPT_LF_FREE,		0xA01, cpt_lf_free, msg_req, msg_rsp)		\













M(CPT_RD_WR_REGISTER,	0xA02, cpt_rd_wr_register,  cpt_rd_wr_reg_msg,	\













			       cpt_rd_wr_reg_msg)			\















/* NPC mbox IDs (range 0x6000 - 0x7FFF) */				\















M(NPC_MCAM_ALLOC_ENTRY,	0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\















				npc_mcam_alloc_entry_rsp)		\










@@ -1046,4 +1051,32 @@ struct ptp_rsp {













	u64 clk;















};





























/* CPT mailbox error codes













 * Range 901 - 1000.













 */













enum cpt_af_status {













	CPT_AF_ERR_PARAM		= -901,













	CPT_AF_ERR_GRP_INVALID		= -902,













	CPT_AF_ERR_LF_INVALID		= -903,













	CPT_AF_ERR_ACCESS_DENIED	= -904,













	CPT_AF_ERR_SSO_PF_FUNC_INVALID	= -905,













	CPT_AF_ERR_NIX_PF_FUNC_INVALID	= -906













};



























/* CPT mbox message formats */













struct cpt_rd_wr_reg_msg {













	struct mbox_msghdr hdr;













	u64 reg_offset;













	u64 *ret_val;













	u64 val;













	u8 is_write;













};



























struct cpt_lf_alloc_req_msg {













	struct mbox_msghdr hdr;













	u16 nix_pf_func;













	u16 sso_pf_func;













	u16 eng_grpmsk;













};





























#endif /* MBOX_H */
























drivers/net/ethernet/marvell/octeontx2/af/rvu.h



+1
−0






























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@@ -52,6 +52,7 @@ struct rvu_debugfs {













	struct dentry *npa;















	struct dentry *nix;















	struct dentry *npc;













	struct dentry *cpt;















	struct dump_ctx npa_aura_ctx;















	struct dump_ctx npa_pool_ctx;















	struct dump_ctx nix_cq_ctx;

































drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
0 → 100644



+233
−0






























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Diff line













// SPDX-License-Identifier: GPL-2.0-only













/* Copyright (C) 2020 Marvell. */



























#include <linux/pci.h>













#include "rvu_struct.h"













#include "rvu_reg.h"













#include "mbox.h"













#include "rvu.h"



























/* CPT PF device id */













#define	PCI_DEVID_OTX2_CPT_PF	0xA0FD



























static int get_cpt_pf_num(struct rvu *rvu)













{













	int i, domain_nr, cpt_pf_num = -1;













	struct pci_dev *pdev;



























	domain_nr = pci_domain_nr(rvu->pdev->bus);













	for (i = 0; i < rvu->hw->total_pfs; i++) {













		pdev = pci_get_domain_bus_and_slot(domain_nr, i + 1, 0);













		if (!pdev)













			continue;



























		if (pdev->device == PCI_DEVID_OTX2_CPT_PF) {













			cpt_pf_num = i;













			put_device(&pdev->dev);













			break;













		}













		put_device(&pdev->dev);













	}













	return cpt_pf_num;













}



























static bool is_cpt_pf(struct rvu *rvu, u16 pcifunc)













{













	int cpt_pf_num = get_cpt_pf_num(rvu);



























	if (rvu_get_pf(pcifunc) != cpt_pf_num)













		return false;













	if (pcifunc & RVU_PFVF_FUNC_MASK)













		return false;



























	return true;













}



























static bool is_cpt_vf(struct rvu *rvu, u16 pcifunc)













{













	int cpt_pf_num = get_cpt_pf_num(rvu);



























	if (rvu_get_pf(pcifunc) != cpt_pf_num)













		return false;













	if (!(pcifunc & RVU_PFVF_FUNC_MASK))













		return false;



























	return true;













}



























int rvu_mbox_handler_cpt_lf_alloc(struct rvu *rvu,













				  struct cpt_lf_alloc_req_msg *req,













				  struct msg_rsp *rsp)













{













	u16 pcifunc = req->hdr.pcifunc;













	struct rvu_block *block;













	int cptlf, blkaddr;













	int num_lfs, slot;













	u64 val;



























	if (req->eng_grpmsk == 0x0)













		return CPT_AF_ERR_GRP_INVALID;



























	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_CPT, 0);













	if (blkaddr < 0)













		return blkaddr;



























	block = &rvu->hw->block[blkaddr];













	num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, pcifunc),













					block->addr);













	if (!num_lfs)













		return CPT_AF_ERR_LF_INVALID;



























	/* Check if requested 'CPTLF <=> NIXLF' mapping is valid */













	if (req->nix_pf_func) {













		/* If default, use 'this' CPTLF's PFFUNC */













		if (req->nix_pf_func == RVU_DEFAULT_PF_FUNC)













			req->nix_pf_func = pcifunc;













		if (!is_pffunc_map_valid(rvu, req->nix_pf_func, BLKTYPE_NIX))













			return CPT_AF_ERR_NIX_PF_FUNC_INVALID;













	}



























	/* Check if requested 'CPTLF <=> SSOLF' mapping is valid */













	if (req->sso_pf_func) {













		/* If default, use 'this' CPTLF's PFFUNC */













		if (req->sso_pf_func == RVU_DEFAULT_PF_FUNC)













			req->sso_pf_func = pcifunc;













		if (!is_pffunc_map_valid(rvu, req->sso_pf_func, BLKTYPE_SSO))













			return CPT_AF_ERR_SSO_PF_FUNC_INVALID;













	}



























	for (slot = 0; slot < num_lfs; slot++) {













		cptlf = rvu_get_lf(rvu, block, pcifunc, slot);













		if (cptlf < 0)













			return CPT_AF_ERR_LF_INVALID;



























		/* Set CPT LF group and priority */













		val = (u64)req->eng_grpmsk << 48 | 1;













		rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf), val);



























		/* Set CPT LF NIX_PF_FUNC and SSO_PF_FUNC */













		val = (u64)req->nix_pf_func << 48 |













		      (u64)req->sso_pf_func << 32;













		rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf), val);













	}



























	return 0;













}



























int rvu_mbox_handler_cpt_lf_free(struct rvu *rvu, struct msg_req *req,













				 struct msg_rsp *rsp)













{













	u16 pcifunc = req->hdr.pcifunc;













	struct rvu_block *block;













	int cptlf, blkaddr;













	int num_lfs, slot;



























	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_CPT, 0);













	if (blkaddr < 0)













		return blkaddr;



























	block = &rvu->hw->block[blkaddr];













	num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, pcifunc),













					block->addr);













	if (!num_lfs)













		return CPT_AF_ERR_LF_INVALID;



























	for (slot = 0; slot < num_lfs; slot++) {













		cptlf = rvu_get_lf(rvu, block, pcifunc, slot);













		if (cptlf < 0)













			return CPT_AF_ERR_LF_INVALID;



























		/* Reset CPT LF group and priority */













		rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf), 0x0);













		/* Reset CPT LF NIX_PF_FUNC and SSO_PF_FUNC */













		rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf), 0x0);













	}



























	return 0;













}



























static bool is_valid_offset(struct rvu *rvu, struct cpt_rd_wr_reg_msg *req)













{













	u64 offset = req->reg_offset;













	int blkaddr, num_lfs, lf;













	struct rvu_block *block;













	struct rvu_pfvf *pfvf;



























	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_CPT, 0);



























	/* Registers that can be accessed from PF/VF */













	if ((offset & 0xFF000) ==  CPT_AF_LFX_CTL(0) ||













	    (offset & 0xFF000) ==  CPT_AF_LFX_CTL2(0)) {













		if (offset & 7)













			return false;



























		lf = (offset & 0xFFF) >> 3;













		block = &rvu->hw->block[blkaddr];













		pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc);













		num_lfs = rvu_get_rsrc_mapcount(pfvf, block->addr);













		if (lf >= num_lfs)













			/* Slot is not valid for that PF/VF */













			return false;



























		/* Translate local LF used by VFs to global CPT LF */













		lf = rvu_get_lf(rvu, &rvu->hw->block[blkaddr],













				req->hdr.pcifunc, lf);













		if (lf < 0)













			return false;



























		return true;













	} else if (!(req->hdr.pcifunc & RVU_PFVF_FUNC_MASK)) {













		/* Registers that can be accessed from PF */













		switch (offset) {













		case CPT_AF_CTL:













		case CPT_AF_PF_FUNC:













		case CPT_AF_BLK_RST:













		case CPT_AF_CONSTANTS1:













			return true;













		}



























		switch (offset & 0xFF000) {













		case CPT_AF_EXEX_STS(0):













		case CPT_AF_EXEX_CTL(0):













		case CPT_AF_EXEX_CTL2(0):













		case CPT_AF_EXEX_UCODE_BASE(0):













			if (offset & 7)













				return false;













			break;













		default:













			return false;













		}













		return true;













	}













	return false;













}



























int rvu_mbox_handler_cpt_rd_wr_register(struct rvu *rvu,













					struct cpt_rd_wr_reg_msg *req,













					struct cpt_rd_wr_reg_msg *rsp)













{













	int blkaddr;



























	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_CPT, 0);













	if (blkaddr < 0)













		return blkaddr;



























	/* This message is accepted only if sent from CPT PF/VF */













	if (!is_cpt_pf(rvu, req->hdr.pcifunc) &&













	    !is_cpt_vf(rvu, req->hdr.pcifunc))













		return CPT_AF_ERR_ACCESS_DENIED;



























	rsp->reg_offset = req->reg_offset;













	rsp->ret_val = req->ret_val;













	rsp->is_write = req->is_write;



























	if (!is_valid_offset(rvu, req))













		return CPT_AF_ERR_ACCESS_DENIED;



























	if (req->is_write)













		rvu_write64(rvu, blkaddr, req->reg_offset, req->val);













	else













		rsp->val = rvu_read64(rvu, blkaddr, req->reg_offset);



























	return 0;













}
































































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