Commit b5f82176 authored by Stafford Horne's avatar Stafford Horne
Browse files

openrisc: use qspinlocks and qrwlocks



Enable OpenRISC to use qspinlocks and qrwlocks for upcoming SMP support.

Signed-off-by: default avatarStafford Horne <shorne@gmail.com>
parent 489e0f80
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+2 −0
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@@ -28,6 +28,8 @@ config OPENRISC
	select OR1K_PIC
	select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
	select NO_BOOTMEM
	select ARCH_USE_QUEUED_SPINLOCKS
	select ARCH_USE_QUEUED_RWLOCKS

config CPU_BIG_ENDIAN
	def_bool y
+4 −0
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@@ -28,6 +28,10 @@ generic-y += module.h
generic-y += pci.h
generic-y += percpu.h
generic-y += preempt.h
generic-y += qspinlock_types.h
generic-y += qspinlock.h
generic-y += qrwlock_types.h
generic-y += qrwlock.h
generic-y += sections.h
generic-y += segment.h
generic-y += string.h
+11 −1
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@@ -19,6 +19,16 @@
#ifndef __ASM_OPENRISC_SPINLOCK_H
#define __ASM_OPENRISC_SPINLOCK_H

#error "or32 doesn't do SMP yet"
#include <asm/qspinlock.h>

#include <asm/qrwlock.h>

#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)

#define arch_spin_relax(lock)	cpu_relax()
#define arch_read_relax(lock)	cpu_relax()
#define arch_write_relax(lock)	cpu_relax()


#endif
+7 −0
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#ifndef _ASM_OPENRISC_SPINLOCK_TYPES_H
#define _ASM_OPENRISC_SPINLOCK_TYPES_H

#include <asm/qspinlock_types.h>
#include <asm/qrwlock_types.h>

#endif /* _ASM_OPENRISC_SPINLOCK_TYPES_H */