Commit b5e02e11 authored by Rob Clark's avatar Rob Clark
Browse files

drm/msm/adreno: un-open-code some packets 



Small cleanup, lets not open-code bits/bitfields that are properly
defined in the rnndb xml (and therefore have builders in the generated
headers)

Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
Reviewed-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent c28c82e9

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

+3 −2
Original line number Diff line number Diff line
@@ -186,7 +186,8 @@ static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, 
	 * timestamp is written to the memory and then triggers the interrupt

	 */

	OUT_PKT7(ring, CP_EVENT_WRITE, 4);

	OUT_RING(ring, CACHE_FLUSH_TS | (1 << 31));

	OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(CACHE_FLUSH_TS) |

		CP_EVENT_WRITE_0_IRQ);

	OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence)));

	OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence)));

	OUT_RING(ring, submit->seqno);
@@ -730,7 +731,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu) 
	 */

	if (adreno_is_a530(adreno_gpu)) {

		OUT_PKT7(gpu->rb[0], CP_EVENT_WRITE, 1);

		OUT_RING(gpu->rb[0], 0x0F);

		OUT_RING(gpu->rb[0], CP_EVENT_WRITE_0_EVENT(STAT_EVENT));



		gpu->funcs->flush(gpu, gpu->rb[0]);

		if (!a5xx_idle(gpu, gpu->rb[0]))

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

+7 −4
Original line number Diff line number Diff line
@@ -74,7 +74,9 @@ static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter, 
		u64 iova)

{

	OUT_PKT7(ring, CP_REG_TO_MEM, 3);

	OUT_RING(ring, counter | (1 << 30) | (2 << 18));

	OUT_RING(ring, CP_REG_TO_MEM_0_REG(counter) |

		CP_REG_TO_MEM_0_CNT(2) |

		CP_REG_TO_MEM_0_64B);

	OUT_RING(ring, lower_32_bits(iova));

	OUT_RING(ring, upper_32_bits(iova));

}
@@ -102,10 +104,10 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, 


	/* Invalidate CCU depth and color */

	OUT_PKT7(ring, CP_EVENT_WRITE, 1);

	OUT_RING(ring, PC_CCU_INVALIDATE_DEPTH);

	OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_DEPTH));



	OUT_PKT7(ring, CP_EVENT_WRITE, 1);

	OUT_RING(ring, PC_CCU_INVALIDATE_COLOR);

	OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_COLOR));



	/* Submit the commands */

	for (i = 0; i < submit->nr_cmds; i++) {
@@ -139,7 +141,8 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, 
	 * timestamp is written to the memory and then triggers the interrupt

	 */

	OUT_PKT7(ring, CP_EVENT_WRITE, 4);

	OUT_RING(ring, CACHE_FLUSH_TS | (1 << 31));

	OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(CACHE_FLUSH_TS) |

		CP_EVENT_WRITE_0_IRQ);

	OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence)));

	OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence)));

	OUT_RING(ring, submit->seqno);

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