Commit b5ddb6d5 authored by Vineet Gupta's avatar Vineet Gupta
Browse files

ARCv2: PAE40: set MSB even if !CONFIG_ARC_HAS_PAE40 but PAE exists in SoC 



PAE40 confiuration in hardware extends some of the address registers
for TLB/cache ops to 2 words.

So far kernel was NOT setting the higher word if feature was not enabled
in software which is wrong. Those need to be set to 0 in such case.

Normally this would be done in the cache flush / tlb ops, however since
these registers only exist conditionally, this would have to be
conditional to a flag being set on boot which is expensive/ugly -
specially for the more common case of PAE exists but not in use.
Optimize that by zero'ing them once at boot - nobody will write to
them afterwards

Cc: stable@vger.kernel.org   #4.4+
Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
parent 7d79cee2

arch/arc/include/asm/mmu.h

+2 −0
Original line number Diff line number Diff line
@@ -94,6 +94,8 @@ static inline int is_pae40_enabled(void) 
	return IS_ENABLED(CONFIG_ARC_HAS_PAE40);

}



extern int pae40_exist_but_not_enab(void);



#endif	/* !__ASSEMBLY__ */



#endif

arch/arc/mm/cache.c

+28 −6
Original line number Diff line number Diff line
@@ -1123,6 +1123,13 @@ noinline void __init arc_ioc_setup(void) 
	__dc_enable();

}



/*

 * Cache related boot time checks/setups only needed on master CPU:

 *  - Geometry checks (kernel build and hardware agree: e.g. L1_CACHE_BYTES)

 *    Assume SMP only, so all cores will have same cache config. A check on

 *    one core suffices for all

 *  - IOC setup / dma callbacks only need to be done once

 */

void __init arc_cache_init_master(void)

{

	unsigned int __maybe_unused cpu = smp_processor_id();
@@ -1202,12 +1209,27 @@ void __ref arc_cache_init(void) 


	printk(arc_cache_mumbojumbo(0, str, sizeof(str)));



	/*

	 * Only master CPU needs to execute rest of function:

	 *  - Assume SMP so all cores will have same cache config so

	 *    any geomtry checks will be same for all

	 *  - IOC setup / dma callbacks only need to be setup once

	 */

	if (!cpu)

		arc_cache_init_master();



	/*

	 * In PAE regime, TLB and cache maintenance ops take wider addresses

	 * And even if PAE is not enabled in kernel, the upper 32-bits still need

	 * to be zeroed to keep the ops sane.

	 * As an optimization for more common !PAE enabled case, zero them out

	 * once at init, rather than checking/setting to 0 for every runtime op

	 */

	if (is_isa_arcv2() && pae40_exist_but_not_enab()) {



		if (IS_ENABLED(CONFIG_ARC_HAS_ICACHE))

			write_aux_reg(ARC_REG_IC_PTAG_HI, 0);



		if (IS_ENABLED(CONFIG_ARC_HAS_DCACHE))

			write_aux_reg(ARC_REG_DC_PTAG_HI, 0);



		if (l2_line_sz) {

			write_aux_reg(ARC_REG_SLC_RGN_END1, 0);

			write_aux_reg(ARC_REG_SLC_RGN_START1, 0);

		}

	}

}

arch/arc/mm/tlb.c

+11 −1
Original line number Diff line number Diff line
@@ -104,6 +104,8 @@ 
/* A copy of the ASID from the PID reg is kept in asid_cache */

DEFINE_PER_CPU(unsigned int, asid_cache) = MM_CTXT_FIRST_CYCLE;



static int __read_mostly pae_exists;



/*

 * Utility Routine to erase a J-TLB entry

 * Caller needs to setup Index Reg (manually or via getIndex)
@@ -784,7 +786,7 @@ void read_decode_mmu_bcr(void) 
		mmu->u_dtlb = mmu4->u_dtlb * 4;

		mmu->u_itlb = mmu4->u_itlb * 4;

		mmu->sasid = mmu4->sasid;

		mmu->pae = mmu4->pae;

		pae_exists = mmu->pae = mmu4->pae;

	}

}
@@ -809,6 +811,11 @@ char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len) 
	return buf;

}



int pae40_exist_but_not_enab(void)

{

	return pae_exists && !is_pae40_enabled();

}



void arc_mmu_init(void)

{

	char str[256];
@@ -859,6 +866,9 @@ void arc_mmu_init(void) 
	/* swapper_pg_dir is the pgd for the kernel, used by vmalloc */

	write_aux_reg(ARC_REG_SCRATCH_DATA0, swapper_pg_dir);

#endif



	if (pae40_exist_but_not_enab())

		write_aux_reg(ARC_REG_TLBPD1HI, 0);

}



/*

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