Commit b5972776 authored by James Ausmus's avatar James Ausmus Committed by Paulo Zanoni
Browse files

drm/i915/icl: Handle expanded PLANE_CTL_FORMAT field 



ICL+ adds changes the PLANE_CTL_FORMAT field from [27:24] to [27:23],
however, all existing PLANE_CTL_FORMAT_* definitions still map to the
correct values.  Add an ICL_PLANE_CTL_FORMAT_MASK definition, and use
that for masking for the conversion to fourcc.

v2: No changes

v3: Change new definition name, drop comment (Rodrigo)

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarJames Ausmus <james.ausmus@intel.com>
Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180130134918.32283-8-paulo.r.zanoni@intel.com
parent 4357ce07

drivers/gpu/drm/i915/i915_reg.h

+6 −0
Original line number Diff line number Diff line
@@ -6349,6 +6349,11 @@ enum { 
#define _PLANE_CTL_3_A				0x70380

#define   PLANE_CTL_ENABLE			(1 << 31)

#define   PLANE_CTL_PIPE_GAMMA_ENABLE		(1 << 30)   /* Pre-GLK */

/*

 * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition

 * expanded to include bit 23 as well. However, the shift-24 based values

 * correctly map to the same formats in ICL, as long as bit 23 is set to 0

 */

#define   PLANE_CTL_FORMAT_MASK			(0xf << 24)

#define   PLANE_CTL_FORMAT_YUV422		(  0 << 24)

#define   PLANE_CTL_FORMAT_NV12			(  1 << 24)
@@ -6358,6 +6363,7 @@ enum { 
#define   PLANE_CTL_FORMAT_AYUV			(  8 << 24)

#define   PLANE_CTL_FORMAT_INDEXED		( 12 << 24)

#define   PLANE_CTL_FORMAT_RGB_565		( 14 << 24)

#define   ICL_PLANE_CTL_FORMAT_MASK		(0x1f << 23)

#define   PLANE_CTL_PIPE_CSC_ENABLE		(1 << 23) /* Pre-GLK */

#define   PLANE_CTL_KEY_ENABLE_MASK		(0x3 << 21)

#define   PLANE_CTL_KEY_ENABLE_SOURCE		(  1 << 21)

drivers/gpu/drm/i915/intel_display.c

+4 −1
Original line number Diff line number Diff line
@@ -8527,6 +8527,9 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc, 


	val = I915_READ(PLANE_CTL(pipe, plane_id));



	if (INTEL_GEN(dev_priv) >= 11)

		pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;

	else

		pixel_format = val & PLANE_CTL_FORMAT_MASK;



	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {

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