Commit b57cb723 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu 

Pull m68knommu arch updates from Greg Ungerer:
 "Includes a cleanup of the non-MMU linker script (it now almost
  exclusively uses the well defined linker script support macros and
  definitions).  Some more merging of MMU and non-MMU common files
  (specifically the arch process.c, ptrace and time.c).  And a big
  cleanup of the massively duplicated ColdFire device definition code.

  Overall we remove about 2000 lines of code, and end up with a single
  set of platform device definitions for the serial ports, ethernet
  ports and QSPI ports common in most ColdFire SoCs.

  I expect you will get a merge conflict on arch/m68k/kernel/process.c,
  in cpu_idle().  It should be relatively strait forward to fixup."

And cpu_idle() conflict resolution was indeed trivial (merging the
nommu/mmu versions of process.c trivially conflicting with the
conversion to use the schedule_preempt_disabled() helper function)

* 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: (57 commits)
  m68knommu: factor more common ColdFire cpu reset code
  m68knommu: make 528x CPU reset register addressing consistent
  m68knommu: make 527x CPU reset register addressing consistent
  m68knommu: make 523x CPU reset register addressing consistent
  m68knommu: factor some common ColdFire cpu reset code
  m68knommu: move old ColdFire timers init from CPU init to timers code
  m68knommu: clean up init code in ColdFire 532x startup
  m68knommu: clean up init code in ColdFire 528x startup
  m68knommu: clean up init code in ColdFire 523x startup
  m68knommu: merge common ColdFire QSPI platform setup code
  m68knommu: make 532x QSPI platform addressing consistent
  m68knommu: make 528x QSPI platform addressing consistent
  m68knommu: make 527x QSPI platform addressing consistent
  m68knommu: make 5249 QSPI platform addressing consistent
  m68knommu: make 523x QSPI platform addressing consistent
  m68knommu: make 520x QSPI platform addressing consistent
  m68knommu: merge common ColdFire FEC platform setup code
  m68knommu: make 532x FEC platform addressing consistent
  m68knommu: make 528x FEC platform addressing consistent
  m68knommu: make 527x FEC platform addressing consistent
  ...
parents ad12ab25 ae909ea4

arch/m68k/Kconfig

+4 −3
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ config M68K 
	select GENERIC_IRQ_SHOW

	select ARCH_HAVE_NMI_SAFE_CMPXCHG if RMW_INSNS

	select GENERIC_CPU_DEVICES

	select FPU if MMU



config RWSEM_GENERIC_SPINLOCK

	bool
@@ -24,9 +25,6 @@ config ARCH_HAS_ILOG2_U64 
config GENERIC_CLOCKEVENTS

	bool



config GENERIC_CMOS_UPDATE

	def_bool !MMU



config GENERIC_GPIO

	bool
@@ -67,6 +65,9 @@ config CPU_HAS_NO_MULDIV64 
config CPU_HAS_ADDRESS_SPACES

	bool



config FPU

	bool



config HZ

	int

	default 1000 if CLEOPATRA

arch/m68k/include/asm/m5206sim.h

+6 −4
Original line number Diff line number Diff line
@@ -100,11 +100,11 @@ 
#define	MCFDMA_BASE1		(MCF_MBAR + 0x240)	/* Base address DMA 1 */



#if defined(CONFIG_NETtel)

#define	MCFUART_BASE1		0x180		/* Base address of UART1 */

#define	MCFUART_BASE2		0x140		/* Base address of UART2 */

#define	MCFUART_BASE0		(MCF_MBAR + 0x180)	/* Base address UART0 */

#define	MCFUART_BASE1		(MCF_MBAR + 0x140)	/* Base address UART1 */

#else

#define	MCFUART_BASE1		0x140		/* Base address of UART1 */

#define	MCFUART_BASE2		0x180		/* Base address of UART2 */

#define	MCFUART_BASE0		(MCF_MBAR + 0x140)	/* Base address UART0 */

#define	MCFUART_BASE1		(MCF_MBAR + 0x180)	/* Base address UART1 */

#endif



/*
@@ -112,6 +112,8 @@ 
 */

#define	MCF_IRQ_TIMER		30		/* Timer0, Level 6 */

#define	MCF_IRQ_PROFILER	31		/* Timer1, Level 7 */

#define	MCF_IRQ_UART0		73		/* UART0 */

#define	MCF_IRQ_UART1		74		/* UART1 */



/*

 *	Generic GPIO

arch/m68k/include/asm/m520xsim.h

+28 −5
Original line number Diff line number Diff line
@@ -48,8 +48,21 @@ 
#define MCFINT_UART1        27          /* Interrupt number for UART1 */

#define MCFINT_UART2        28          /* Interrupt number for UART2 */

#define MCFINT_QSPI         31          /* Interrupt number for QSPI */

#define MCFINT_FECRX0	    36		/* Interrupt number for FEC RX */

#define MCFINT_FECTX0	    40		/* Interrupt number for FEC RX */

#define MCFINT_FECENTC0	    42		/* Interrupt number for FEC RX */

#define MCFINT_PIT1         4           /* Interrupt number for PIT1 (PIT0 in processor) */



#define MCF_IRQ_UART0	    (MCFINT_VECBASE + MCFINT_UART0)

#define MCF_IRQ_UART1	    (MCFINT_VECBASE + MCFINT_UART1)

#define MCF_IRQ_UART2	    (MCFINT_VECBASE + MCFINT_UART2)



#define MCF_IRQ_FECRX0	    (MCFINT_VECBASE + MCFINT_FECRX0)

#define MCF_IRQ_FECTX0	    (MCFINT_VECBASE + MCFINT_FECTX0)

#define MCF_IRQ_FECENTC0    (MCFINT_VECBASE + MCFINT_FECENTC0)



#define	MCF_IRQ_QSPI	    (MCFINT_VECBASE + MCFINT_QSPI)



/*

 *  SDRAM configuration registers.

 */
@@ -144,15 +157,25 @@ 
/*

 *  UART module.

 */

#define MCFUART_BASE1		0xFC060000	/* Base address of UART1 */

#define MCFUART_BASE2		0xFC064000	/* Base address of UART2 */

#define MCFUART_BASE3		0xFC068000	/* Base address of UART2 */

#define MCFUART_BASE0		0xFC060000	/* Base address of UART0 */

#define MCFUART_BASE1		0xFC064000	/* Base address of UART1 */

#define MCFUART_BASE2		0xFC068000	/* Base address of UART2 */



/*

 *  FEC module.

 */

#define	MCFFEC_BASE		0xFC030000	/* Base of FEC ethernet */

#define	MCFFEC_SIZE		0x800		/* Register set size */

#define	MCFFEC_BASE0		0xFC030000	/* Base of FEC ethernet */

#define	MCFFEC_SIZE0		0x800		/* Register set size */



/*

 *  QSPI module.

 */

#define	MCFQSPI_BASE		0xFC05C000	/* Base of QSPI module */

#define	MCFQSPI_SIZE		0x40		/* Register set size */



#define	MCFQSPI_CS0		46

#define	MCFQSPI_CS1		47

#define	MCFQSPI_CS2		27



/*

 *  Reset Control Unit.

arch/m68k/include/asm/m523xsim.h

+34 −8
Original line number Diff line number Diff line
@@ -35,8 +35,23 @@ 


#define	MCFINT_VECBASE		64		/* Vector base number */

#define	MCFINT_UART0		13		/* Interrupt number for UART0 */

#define	MCFINT_PIT1		36		/* Interrupt number for PIT1 */

#define	MCFINT_UART1		14		/* Interrupt number for UART1 */

#define	MCFINT_UART2		15		/* Interrupt number for UART2 */

#define MCFINT_QSPI		18		/* Interrupt number for QSPI */

#define	MCFINT_FECRX0		23		/* Interrupt number for FEC */

#define	MCFINT_FECTX0		27		/* Interrupt number for FEC */

#define	MCFINT_FECENTC0		29		/* Interrupt number for FEC */

#define	MCFINT_PIT1		36		/* Interrupt number for PIT1 */



#define	MCF_IRQ_UART0	        (MCFINT_VECBASE + MCFINT_UART0)

#define	MCF_IRQ_UART1	        (MCFINT_VECBASE + MCFINT_UART1)

#define	MCF_IRQ_UART2	        (MCFINT_VECBASE + MCFINT_UART2)



#define	MCF_IRQ_FECRX0		(MCFINT_VECBASE + MCFINT_FECRX0)

#define	MCF_IRQ_FECTX0		(MCFINT_VECBASE + MCFINT_FECTX0)

#define	MCF_IRQ_FECENTC0	(MCFINT_VECBASE + MCFINT_FECENTC0)



#define	MCF_IRQ_QSPI		(MCFINT_VECBASE + MCFINT_QSPI)



/*

 *	SDRAM configuration registers.
@@ -50,8 +65,8 @@ 
/*

 *  Reset Control Unit (relative to IPSBAR).

 */

#define	MCF_RCR			0x110000

#define	MCF_RSR			0x110001

#define	MCF_RCR			(MCF_IPSBAR + 0x110000)

#define	MCF_RSR			(MCF_IPSBAR + 0x110001)



#define	MCF_RCR_SWRESET		0x80		/* Software reset bit */

#define	MCF_RCR_FRCSTOUT	0x40		/* Force external reset */
@@ -59,15 +74,26 @@ 
/*

 *  UART module.

 */

#define MCFUART_BASE1		(MCF_IPSBAR + 0x200)

#define MCFUART_BASE2		(MCF_IPSBAR + 0x240)

#define MCFUART_BASE3		(MCF_IPSBAR + 0x280)

#define MCFUART_BASE0		(MCF_IPSBAR + 0x200)

#define MCFUART_BASE1		(MCF_IPSBAR + 0x240)

#define MCFUART_BASE2		(MCF_IPSBAR + 0x280)



/*

 *  FEC ethernet module.

 */

#define	MCFFEC_BASE		(MCF_IPSBAR + 0x1000)

#define	MCFFEC_SIZE		0x800

#define	MCFFEC_BASE0		(MCF_IPSBAR + 0x1000)

#define	MCFFEC_SIZE0		0x800



/*

 *  QSPI module.

 */

#define	MCFQSPI_BASE		(MCF_IPSBAR + 0x340)

#define	MCFQSPI_SIZE		0x40



#define	MCFQSPI_CS0		91

#define	MCFQSPI_CS1		92

#define	MCFQSPI_CS2		103

#define	MCFQSPI_CS3		99



/*

 *  GPIO module.

arch/m68k/include/asm/m5249sim.h

+16 −2
Original line number Diff line number Diff line
@@ -76,8 +76,19 @@ 
/*

 *	UART module.

 */

#define MCFUART_BASE1		0x1c0           /* Base address of UART1 */

#define MCFUART_BASE2		0x200           /* Base address of UART2 */

#define MCFUART_BASE0		(MCF_MBAR + 0x1c0)	/* Base address UART0 */

#define MCFUART_BASE1		(MCF_MBAR + 0x200)	/* Base address UART1 */



/*

 *	QSPI module.

 */

#define	MCFQSPI_BASE		(MCF_MBAR + 0x300)	/* Base address QSPI */

#define	MCFQSPI_SIZE		0x40			/* Register set size */



#define	MCFQSPI_CS0		29

#define	MCFQSPI_CS1		24

#define	MCFQSPI_CS2		21

#define	MCFQSPI_CS3		22



/*

 *	DMA unit base addresses.
@@ -108,6 +119,9 @@ 
#define	MCF_IRQ_TIMER		30		/* Timer0, Level 6 */

#define	MCF_IRQ_PROFILER	31		/* Timer1, Level 7 */



#define	MCF_IRQ_UART0		73		/* UART0 */

#define	MCF_IRQ_UART1		74		/* UART1 */



/*

 *	General purpose IO registers (in MBAR2).

 */

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