Commit b5512b45 authored by Bill Huang's avatar Bill Huang Committed by Thierry Reding
Browse files

clk: tegra: pll: Adjust vco_min if SDM present 



This code makes use of the SDM fractional divider if present to
constrain the allowable programming range of the PLL divider register
bitfields to take advantage of higher frequency granularity that can
be induced by the SDM divider.

Based on original work by Aleksandr Frid <afrid@nvidia.com>

Signed-off-by: default avatarBill Huang <bilhuang@nvidia.com>
Signed-off-by: default avatarRhyland Klein <rklein@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 6929715c

drivers/clk/tegra/clk-pll.c

+28 −0
Original line number Diff line number Diff line
@@ -1621,6 +1621,10 @@ struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, 


	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);



	if (pll_params->adjust_vco)

		pll_params->vco_min = pll_params->adjust_vco(pll_params,

							     parent_rate);



	err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate);

	if (err)

		return ERR_PTR(err);
@@ -1659,6 +1663,10 @@ struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, 


	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);



	if (pll_params->adjust_vco)

		pll_params->vco_min = pll_params->adjust_vco(pll_params,

							     parent_rate);



	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);

	if (IS_ERR(pll))

		return ERR_CAST(pll);
@@ -1715,6 +1723,10 @@ struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, 


	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);



	if (pll_params->adjust_vco)

		pll_params->vco_min = pll_params->adjust_vco(pll_params,

							     parent_rate);



	pll_params->flags |= TEGRA_PLL_BYPASS;

	pll_params->flags |= TEGRA_PLLM;

	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
@@ -2121,6 +2133,10 @@ struct clk *tegra_clk_register_pllc_tegra210(const char *name, 


	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);



	if (pll_params->adjust_vco)

		pll_params->vco_min = pll_params->adjust_vco(pll_params,

							     parent_rate);



	pll_params->flags |= TEGRA_PLL_BYPASS;

	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);

	if (IS_ERR(pll))
@@ -2158,6 +2174,10 @@ struct clk *tegra_clk_register_pllxc_tegra210(const char *name, 


	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);



	if (pll_params->adjust_vco)

		pll_params->vco_min = pll_params->adjust_vco(pll_params,

							     parent_rate);



	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);

	if (IS_ERR(pll))

		return ERR_CAST(pll);
@@ -2205,6 +2225,10 @@ struct clk *tegra_clk_register_pllss_tegra210(const char *name, 


	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);



	if (pll_params->adjust_vco)

		pll_params->vco_min = pll_params->adjust_vco(pll_params,

							     parent_rate);



	/* initialize PLL to minimum rate */



	cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
@@ -2269,6 +2293,10 @@ struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name, 


	pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);



	if (pll_params->adjust_vco)

		pll_params->vco_min = pll_params->adjust_vco(pll_params,

							     parent_rate);



	pll_params->flags |= TEGRA_PLL_BYPASS;

	pll_params->flags |= TEGRA_PLLMB;

	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);

drivers/clk/tegra/clk.h

+4 −0
Original line number Diff line number Diff line
@@ -202,6 +202,8 @@ struct div_nmp { 
 *				PLL's based on fractional divider value.

 * @calc_rate:			Callback used to change how out of table

 *				rates (dividers and multipler) are calculated.

 * @adjust_vco:			Callback to adjust the programming range of the

 *				divider range (if SDM is present)

 *

 * Flags:

 * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for
@@ -269,6 +271,8 @@ struct tegra_clk_pll_params { 
	int	(*calc_rate)(struct clk_hw *hw,

			struct tegra_clk_pll_freq_table *cfg,

			unsigned long rate, unsigned long parent_rate);

	unsigned long	(*adjust_vco)(struct tegra_clk_pll_params *pll_params,

				unsigned long parent_rate);

};



#define TEGRA_PLL_USE_LOCK BIT(0)

CRA Git | Maintained and supported by SUSTech CRA and CCSE