Commit b530602f authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon: add audio support for DCE6/8 GPUs (v12) 



Similar to DCE4/5, but supports multiple audio pins
which can be assigned per afmt block.

v2: rework the driver to handle more than one audio
pin.
v3: try different dto reg
v4: properly program dto
v5 (ck): change dto programming order
v6: program speaker allocation block
v7: rebase
v8: rebase on Rafał's changes
v9: integrated Rafał's comments, update to latest
    drm_edid_to_speaker_allocation API
v10: add missing line break in error message
v11: add back audio enabled messages
v12: fix copy paste typo in r600_audio_enable

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Acked-by: default avatarRafał Miłecki <zajec5@gmail.com>
parent a4d39e68

drivers/gpu/drm/radeon/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -80,7 +80,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \ 
	r600_dpm.o rs780_dpm.o rv6xx_dpm.o rv770_dpm.o rv730_dpm.o rv740_dpm.o \

	rv770_smc.o cypress_dpm.o btc_dpm.o sumo_dpm.o sumo_smc.o trinity_dpm.o \

	trinity_smc.o ni_dpm.o si_smc.o si_dpm.o kv_smc.o kv_dpm.o ci_smc.o \

	ci_dpm.o

	ci_dpm.o dce6_afmt.o



# add async DMA block

radeon-y += \

drivers/gpu/drm/radeon/atombios_encoders.c

+3 −8
Original line number Diff line number Diff line
@@ -682,8 +682,6 @@ atombios_digital_setup(struct drm_encoder *encoder, int action) 
int

atombios_get_encoder_mode(struct drm_encoder *encoder)

{

	struct drm_device *dev = encoder->dev;

	struct radeon_device *rdev = dev->dev_private;

	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);

	struct drm_connector *connector;

	struct radeon_connector *radeon_connector;
@@ -710,8 +708,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder) 
	case DRM_MODE_CONNECTOR_DVII:

	case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */

		if (drm_detect_hdmi_monitor(radeon_connector->edid) &&

		    radeon_audio &&

		    !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */

		    radeon_audio)

			return ATOM_ENCODER_MODE_HDMI;

		else if (radeon_connector->use_digital)

			return ATOM_ENCODER_MODE_DVI;
@@ -722,8 +719,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder) 
	case DRM_MODE_CONNECTOR_HDMIA:

	default:

		if (drm_detect_hdmi_monitor(radeon_connector->edid) &&

		    radeon_audio &&

		    !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */

		    radeon_audio)

			return ATOM_ENCODER_MODE_HDMI;

		else

			return ATOM_ENCODER_MODE_DVI;
@@ -737,8 +733,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder) 
		    (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))

			return ATOM_ENCODER_MODE_DP;

		else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&

			 radeon_audio &&

			 !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */

			 radeon_audio)

			return ATOM_ENCODER_MODE_HDMI;

		else

			return ATOM_ENCODER_MODE_DVI;

drivers/gpu/drm/radeon/cik.c

+5 −0
Original line number Diff line number Diff line
@@ -7004,6 +7004,10 @@ static int cik_startup(struct radeon_device *rdev) 
		return r;

	}



	r = dce6_audio_init(rdev);

	if (r)

		return r;



	return 0;

}
@@ -7049,6 +7053,7 @@ int cik_resume(struct radeon_device *rdev) 
 */

int cik_suspend(struct radeon_device *rdev)

{

	dce6_audio_fini(rdev);

	radeon_vm_manager_fini(rdev);

	cik_cp_enable(rdev, false);

	cik_sdma_enable(rdev, false);

drivers/gpu/drm/radeon/dce6_afmt.c

0 → 100644
+251 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2013 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */

#include <linux/hdmi.h>

#include <drm/drmP.h>

#include "radeon.h"

#include "sid.h"



static u32 dce6_endpoint_rreg(struct radeon_device *rdev,

			      u32 block_offset, u32 reg)

{

	u32 r;



	WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);

	r = RREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset);

	return r;

}



static void dce6_endpoint_wreg(struct radeon_device *rdev,

			       u32 block_offset, u32 reg, u32 v)

{

	if (ASIC_IS_DCE8(rdev))

		WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);

	else

		WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset,

		       AZ_ENDPOINT_REG_WRITE_EN | AZ_ENDPOINT_REG_INDEX(reg));

	WREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset, v);

}



#define RREG32_ENDPOINT(block, reg) dce6_endpoint_rreg(rdev, (block), (reg))

#define WREG32_ENDPOINT(block, reg, v) dce6_endpoint_wreg(rdev, (block), (reg), (v))





static void dce6_afmt_get_connected_pins(struct radeon_device *rdev)

{

	int i;

	u32 offset, tmp;



	for (i = 0; i < rdev->audio.num_pins; i++) {

		offset = rdev->audio.pin[i].offset;

		tmp = RREG32_ENDPOINT(offset,

				      AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);

		if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1)

			rdev->audio.pin[i].connected = false;

		else

			rdev->audio.pin[i].connected = true;

	}

}



struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev)

{

	int i;



	dce6_afmt_get_connected_pins(rdev);



	for (i = 0; i < rdev->audio.num_pins; i++) {

		if (rdev->audio.pin[i].connected)

			return &rdev->audio.pin[i];

	}

	DRM_ERROR("No connected audio pins found!\n");

	return NULL;

}



void dce6_afmt_select_pin(struct drm_encoder *encoder)

{

	struct radeon_device *rdev = encoder->dev->dev_private;

	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);

	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;

	u32 offset = dig->afmt->offset;

	u32 id = dig->afmt->pin->id;



	if (!dig->afmt->pin)

		return;



	WREG32(AFMT_AUDIO_SRC_CONTROL + offset, AFMT_AUDIO_SRC_SELECT(id));

}



void dce6_afmt_write_sad_regs(struct drm_encoder *encoder)

{

	struct radeon_device *rdev = encoder->dev->dev_private;

	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);

	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;

	u32 offset, tmp;

	struct drm_connector *connector;

	struct radeon_connector *radeon_connector = NULL;

	struct cea_sad *sads;

	int i, sad_count, sadb_count;

	u8 *sadb;



	static const u16 eld_reg_to_type[][2] = {

		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },

		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },

		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },

		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },

		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },

		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },

		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },

		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },

		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },

		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },

		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },

		{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },

	};



	if (!dig->afmt->pin)

		return;



	offset = dig->afmt->pin->offset;



	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {

		if (connector->encoder == encoder)

			radeon_connector = to_radeon_connector(connector);

	}



	if (!radeon_connector) {

		DRM_ERROR("Couldn't find encoder's connector\n");

		return;

	}



	sad_count = drm_edid_to_sad(radeon_connector->edid, &sads);

	if (sad_count < 0) {

		DRM_ERROR("Couldn't read SADs: %d\n", sad_count);

		return;

	}

	BUG_ON(!sads);



	sadb_count = drm_edid_to_speaker_allocation(radeon_connector->edid, &sadb);

	if (sadb_count < 0) {

		DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sadb_count);

		return;

	}



	/* program the speaker allocation */

	tmp = RREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);

	tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);

	/* set HDMI mode */

	tmp |= HDMI_CONNECTION;

	if (sadb_count)

		tmp |= SPEAKER_ALLOCATION(sadb[0]);

	else

		tmp |= SPEAKER_ALLOCATION(5); /* stereo */

	WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);



	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {

		u32 value = 0;

		int j;



		for (j = 0; j < sad_count; j++) {

			struct cea_sad *sad = &sads[j];



			if (sad->format == eld_reg_to_type[i][1]) {

				value = MAX_CHANNELS(sad->channels) |

					DESCRIPTOR_BYTE_2(sad->byte2) |

					SUPPORTED_FREQUENCIES(sad->freq);

				if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)

					value |= SUPPORTED_FREQUENCIES_STEREO(sad->freq);

				break;

			}

		}

		WREG32_ENDPOINT(offset, eld_reg_to_type[i][0], value);

	}



	kfree(sads);

	kfree(sadb);

}



static int dce6_audio_chipset_supported(struct radeon_device *rdev)

{

	return !ASIC_IS_NODCE(rdev);

}



static void dce6_audio_enable(struct radeon_device *rdev,

			      struct r600_audio_pin *pin,

			      bool enable)

{

	WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOTPLUG_CONTROL,

			AUDIO_ENABLED);

	DRM_INFO("%s audio %d support\n", enable ? "Enabling" : "Disabling", pin->id);

}



static const u32 pin_offsets[7] =

{

	(0x5e00 - 0x5e00),

	(0x5e18 - 0x5e00),

	(0x5e30 - 0x5e00),

	(0x5e48 - 0x5e00),

	(0x5e60 - 0x5e00),

	(0x5e78 - 0x5e00),

	(0x5e90 - 0x5e00),

};



int dce6_audio_init(struct radeon_device *rdev)

{

	int i;



	if (!radeon_audio || !dce6_audio_chipset_supported(rdev))

		return 0;



	rdev->audio.enabled = true;



	if (ASIC_IS_DCE8(rdev))

		rdev->audio.num_pins = 7;

	else

		rdev->audio.num_pins = 6;



	for (i = 0; i < rdev->audio.num_pins; i++) {

		rdev->audio.pin[i].channels = -1;

		rdev->audio.pin[i].rate = -1;

		rdev->audio.pin[i].bits_per_sample = -1;

		rdev->audio.pin[i].status_bits = 0;

		rdev->audio.pin[i].category_code = 0;

		rdev->audio.pin[i].connected = false;

		rdev->audio.pin[i].offset = pin_offsets[i];

		rdev->audio.pin[i].id = i;

		dce6_audio_enable(rdev, &rdev->audio.pin[i], true);

	}



	return 0;

}



void dce6_audio_fini(struct radeon_device *rdev)

{

	int i;



	if (!rdev->audio.enabled)

		return;



	for (i = 0; i < rdev->audio.num_pins; i++)

		dce6_audio_enable(rdev, &rdev->audio.pin[i], false);



	rdev->audio.enabled = false;

}

drivers/gpu/drm/radeon/evergreen_hdmi.c

+39 −15
Original line number Diff line number Diff line
@@ -32,6 +32,9 @@ 
#include "evergreend.h"

#include "atom.h"



extern void dce6_afmt_write_sad_regs(struct drm_encoder *encoder);

extern void dce6_afmt_select_pin(struct drm_encoder *encoder);



/*

 * update the N and CTS parameters for a given pixel clock rate

 */
@@ -157,6 +160,9 @@ static void evergreen_audio_set_dto(struct drm_encoder *encoder, u32 clock) 
	if (!dig || !dig->afmt)

		return;



	if (ASIC_IS_DCE6(rdev)) {

		dto_phase = 24 * 1000;

	} else {

		if (max_ratio >= 8) {

			dto_phase = 192 * 1000;

			wallclock_ratio = 3;
@@ -173,6 +179,7 @@ static void evergreen_audio_set_dto(struct drm_encoder *encoder, u32 clock) 
		dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;

		dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);

		WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl);

	}



	/* XXX two dtos; generally use dto0 for hdmi */

	/* Express [24MHz / target pixel clock] as an exact rational
@@ -266,7 +273,13 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode 
	       AFMT_AUDIO_CHANNEL_ENABLE(0xff));



	/* fglrx sets 0x40 in 0x5f80 here */



	if (ASIC_IS_DCE6(rdev)) {

		dce6_afmt_select_pin(encoder);

		dce6_afmt_write_sad_regs(encoder);

	} else {

		evergreen_hdmi_write_sad_regs(encoder);

	}



	err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);

	if (err < 0) {
@@ -302,6 +315,8 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode 


void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)

{

	struct drm_device *dev = encoder->dev;

	struct radeon_device *rdev = dev->dev_private;

	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);

	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
@@ -314,6 +329,15 @@ void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable) 
	if (!enable && !dig->afmt->enabled)

		return;



	if (enable) {

		if (ASIC_IS_DCE6(rdev))

			dig->afmt->pin = dce6_audio_get_pin(rdev);

		else

			dig->afmt->pin = r600_audio_get_pin(rdev);

	} else {

		dig->afmt->pin = NULL;

	}



	dig->afmt->enabled = enable;



	DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",

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