Commit b51ecc0a authored by Chunfeng Yun's avatar Chunfeng Yun Committed by Kishon Vijay Abraham I
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dt-bindings: phy-mtk-tphy: make the ref clock optional 



Make the ref clock optional, then we no need refer to a fixed-clock
in DTS anymore when the clock of USB3 PHY comes from oscillator
directly

Signed-off-by: default avatarChunfeng Yun <chunfeng.yun@mediatek.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
parent 6e6fed24

Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt

+7 −6
Original line number Diff line number Diff line
@@ -34,12 +34,6 @@ Optional properties (controller (parent) node): 


Required properties (port (child) node):

- reg		: address and length of the register set for the port.

- clocks	: a list of phandle + clock-specifier pairs, one for each

		  entry in clock-names

- clock-names	: must contain

		  "ref": 48M reference clock for HighSpeed analog phy; and 26M

			reference clock for SuperSpeed analog phy, sometimes is

			24M, 25M or 27M, depended on platform.

- #phy-cells	: should be 1 (See second example)

		  cell after port phandle is phy type from:

			- PHY_TYPE_USB2
@@ -48,6 +42,13 @@ Required properties (port (child) node): 
			- PHY_TYPE_SATA



Optional properties (PHY_TYPE_USB2 port (child) node):

- clocks	: a list of phandle + clock-specifier pairs, one for each

		  entry in clock-names

- clock-names	: may contain

		  "ref": 48M reference clock for HighSpeed anolog phy; and 26M

			reference clock for SuperSpeed anolog phy, sometimes is

			24M, 25M or 27M, depended on platform.



- mediatek,eye-src	: u32, the value of slew rate calibrate

- mediatek,eye-vrt	: u32, the selection of VRT reference voltage

- mediatek,eye-term	: u32, the selection of HS_TX TERM reference voltage

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