PM / devfreq: exynos-bus: Add the detailed correlation for Exynos5433 (b5136524) · Commits · 戴 / test

This patch adds the detailed corrleation between sub-blocks and VDD_INT power line for Exynos5433. VDD_INT provided the power source to INT (Internal) block. Signed-off-by:

Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by:

MyungJoo Ham <myungjoo.ham@samsung.com>

Documentation/devicetree/bindings/devfreq/exynos-bus.txt

+14 −0

Original line number	Diff line number	Diff line
		@@ -123,6 +123,20 @@ Detailed correlation between sub-blocks and power line according to Exynos SoC:
		\|--- FSYS
		\|--- FSYS2

		- In case of Exynos5433, there is VDD_INT power line as following:
		VDD_INT \|--- G2D (parent device)
		\|--- MSCL
		\|--- GSCL
		\|--- JPEG
		\|--- MFC
		\|--- HEVC
		\|--- BUS0
		\|--- BUS1
		\|--- BUS2
		\|--- PERIS (Fixed clock rate)
		\|--- PERIC (Fixed clock rate)
		\|--- FSYS (Fixed clock rate)

		Example1:
		Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to
		power line (regulator). The MIF (Memory Interface) AXI bus is used to

Admin message