Commit b4f99176 authored by Sowjanya Komatineni's avatar Sowjanya Komatineni Committed by Thierry Reding
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arm64: tegra: Fix SOR powergate clocks and reset 



Tegra210 device tree lists CSI clock and reset under SOR powergate
node.

But Tegra210 has CSICIL in SOR partition and CSI in VENC partition.

So, this patch includes fix for SOR powergate node.

Signed-off-by: default avatarSowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 4012ab12

arch/arm64/boot/dts/nvidia/tegra210.dtsi

+3 −2
Original line number Diff line number Diff line
@@ -796,7 +796,9 @@ 
			pd_sor: sor {

				clocks = <&tegra_car TEGRA210_CLK_SOR0>,

					 <&tegra_car TEGRA210_CLK_SOR1>,

					 <&tegra_car TEGRA210_CLK_CSI>,

					 <&tegra_car TEGRA210_CLK_CILAB>,

					 <&tegra_car TEGRA210_CLK_CILCD>,

					 <&tegra_car TEGRA210_CLK_CILE>,

					 <&tegra_car TEGRA210_CLK_DSIA>,

					 <&tegra_car TEGRA210_CLK_DSIB>,

					 <&tegra_car TEGRA210_CLK_DPAUX>,
@@ -804,7 +806,6 @@ 
					 <&tegra_car TEGRA210_CLK_MIPI_CAL>;

				resets = <&tegra_car TEGRA210_CLK_SOR0>,

					 <&tegra_car TEGRA210_CLK_SOR1>,

					 <&tegra_car TEGRA210_CLK_CSI>,

					 <&tegra_car TEGRA210_CLK_DSIA>,

					 <&tegra_car TEGRA210_CLK_DSIB>,

					 <&tegra_car TEGRA210_CLK_DPAUX>,

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