Commit b4f2d7c3 authored by Thomas Gleixner's avatar Thomas Gleixner
Browse files

Merge tag 'irqchip-for-4.11' of... 

Merge tag 'irqchip-for-4.11' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core

Pull irqchip updates for 4.11 from Marc Zyngier

- A number of gic-v3-its cleanups and fixes
- A fix for the MIPS GIC
- One new interrupt controller for the Cortina Gemini platform
- Support for the Qualcomm interrupt combiner, together with
  its ACPI goodness
parents 788d2393 34d677a9

Documentation/devicetree/bindings/interrupt-controller/cortina,gemini-interrupt-controller.txt

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* Cortina Systems Gemini interrupt controller



This interrupt controller is found on the Gemini SoCs.



Required properties:

- compatible: must be "cortina,gemini-interrupt-controller"

- reg: The register bank for the interrupt controller.

- interrupt-controller: Identifies the node as an interrupt controller

- #interrupt-cells: The number of cells to define the interrupts.

  Must be 2 as the controller can specify level or rising edge

  IRQs. The bindings follows the standard binding for controllers

  with two cells specified in

  interrupt-controller/interrupts.txt



Example:



interrupt-controller@48000000 {

	compatible = "cortina,gemini-interrupt-controller";

	reg = <0x48000000 0x1000>;

	interrupt-controller;

	#interrupt-cells = <2>;

};

Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt

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@@ -15,6 +15,9 @@ Properties: 
  Second cell specifies the irq distribution mode to cores

     0=Round Robin; 1=cpu0, 2=cpu1, 4=cpu2, 8=cpu3



  The second cell in interrupts property is deprecated and may be ignored by

  the kernel.



  intc accessed via the special ARC AUX register interface, hence "reg" property

  is not specified.

Documentation/devicetree/bindings/mtd/tango-nand.txt

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@@ -5,7 +5,7 @@ Required properties: 
- compatible: "sigma,smp8758-nand"

- reg: address/size of nfc_reg, nfc_mem, and pbus_reg

- dmas: reference to the DMA channel used by the controller

- dma-names: "nfc_sbox"

- dma-names: "rxtx"

- clocks: reference to the system clock

- #address-cells: <1>

- #size-cells: <0>
@@ -17,9 +17,9 @@ Example: 


	nandc: nand-controller@2c000 {

		compatible = "sigma,smp8758-nand";

		reg = <0x2c000 0x30 0x2d000 0x800 0x20000 0x1000>;

		reg = <0x2c000 0x30>, <0x2d000 0x800>, <0x20000 0x1000>;

		dmas = <&dma0 3>;

		dma-names = "nfc_sbox";

		dma-names = "rxtx";

		clocks = <&clkgen SYS_CLK>;

		#address-cells = <1>;

		#size-cells = <0>;

Documentation/devicetree/bindings/net/mediatek-net.txt

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@@ -7,7 +7,7 @@ have dual GMAC each represented by a child node.. 
* Ethernet controller node



Required properties:

- compatible: Should be "mediatek,mt7623-eth"

- compatible: Should be "mediatek,mt2701-eth"

- reg: Address and length of the register set for the device

- interrupts: Should contain the three frame engines interrupts in numeric

	order. These are fe_int0, fe_int1 and fe_int2.

Documentation/devicetree/bindings/net/phy.txt

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@@ -19,8 +19,9 @@ Optional Properties: 
  specifications. If neither of these are specified, the default is to

  assume clause 22.



  If the phy's identifier is known then the list may contain an entry

  of the form: "ethernet-phy-idAAAA.BBBB" where

  If the PHY reports an incorrect ID (or none at all) then the

  "compatible" list may contain an entry with the correct PHY ID in the

  form: "ethernet-phy-idAAAA.BBBB" where

     AAAA - The value of the 16 bit Phy Identifier 1 register as

            4 hex digits. This is the chip vendor OUI bits 3:18

     BBBB - The value of the 16 bit Phy Identifier 2 register as

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