Merge tag 'pinctrl-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl (b4e1bce8) · Commits · 戴 / test

Documentation/devicetree/bindings/pinctrl/actions,s500-pinctrl.yaml

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		# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
		%YAML 1.2
		---
		$id: http://devicetree.org/schemas/pinctrl/actions,s500-pinctrl.yaml#
		$schema: http://devicetree.org/meta-schemas/core.yaml#

		title: Actions Semi S500 SoC pinmux & GPIO controller

		maintainers:
		- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
		- Cristian Ciocaltea <cristian.ciocaltea@gmail.com>

		description: \|
		Pinmux & GPIO controller manages pin multiplexing & configuration including
		GPIO function selection & GPIO attributes configuration. Please refer to
		pinctrl-bindings.txt in this directory for common binding part and usage.

		properties:
		compatible:
		const: actions,s500-pinctrl

		reg:
		items:
		- description: GPIO Output + GPIO Input + GPIO Data
		- description: Multiplexing Control
		- description: PAD Pull Control + PAD Schmitt Trigger Enable + PAD Control
		- description: PAD Drive Capacity Select
		minItems: 1
		maxItems: 4

		clocks:
		maxItems: 1

		gpio-controller: true

		gpio-ranges:
		maxItems: 1

		'#gpio-cells':
		description:
		Specifies the pin number and flags, as defined in
		include/dt-bindings/gpio/gpio.h
		const: 2

		interrupt-controller: true

		'#interrupt-cells':
		description:
		Specifies the pin number and flags, as defined in
		include/dt-bindings/interrupt-controller/irq.h
		const: 2

		interrupts:
		description:
		One interrupt per each of the 5 GPIO ports supported by the controller,
		sorted by port number ascending order.
		minItems: 5
		maxItems: 5

		patternProperties:
		'-pins$':
		type: object
		patternProperties:
		'^(.*-)?pinmux$':
		type: object
		description:
		Pinctrl node's client devices specify pin muxes using subnodes,
		which in turn use the standard properties below.
		$ref: pinmux-node.yaml#

		properties:
		groups:
		description:
		List of gpio pin groups affected by the functions specified in
		this subnode.
		items:
		oneOf:
		- enum: [lcd0_d18_mfp, rmii_crs_dv_mfp, rmii_txd0_mfp,
		rmii_txd1_mfp, rmii_txen_mfp, rmii_rxen_mfp, rmii_rxd1_mfp,
		rmii_rxd0_mfp, rmii_ref_clk_mfp, i2s_d0_mfp, i2s_pcm1_mfp,
		i2s0_pcm0_mfp, i2s1_pcm0_mfp, i2s_d1_mfp, ks_in2_mfp,
		ks_in1_mfp, ks_in0_mfp, ks_in3_mfp, ks_out0_mfp,
		ks_out1_mfp, ks_out2_mfp, lvds_o_pn_mfp, dsi_dn0_mfp,
		dsi_dp2_mfp, lcd0_d17_mfp, dsi_dp3_mfp, dsi_dn3_mfp,
		dsi_dp0_mfp, lvds_ee_pn_mfp, spi0_i2c_pcm_mfp,
		spi0_i2s_pcm_mfp, dsi_dnp1_cp_mfp, lvds_e_pn_mfp,
		dsi_dn2_mfp, uart2_rtsb_mfp, uart2_ctsb_mfp, uart3_rtsb_mfp,
		uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp, sd0_d2_d3_mfp,
		sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_mfp,
		uart0_rx_mfp, clko_25m_mfp, csi_cn_cp_mfp, sens0_ckout_mfp,
		uart0_tx_mfp, i2c0_mfp, csi_dn_dp_mfp, sen0_pclk_mfp,
		pcm1_in_mfp, pcm1_clk_mfp, pcm1_sync_mfp, pcm1_out_mfp,
		dnand_data_wr_mfp, dnand_acle_ce0_mfp, nand_ceb2_mfp,
		nand_ceb3_mfp]
		minItems: 1
		maxItems: 32

		function:
		description:
		Specify the alternative function to be configured for the
		given gpio pin groups.
		enum: [nor, eth_rmii, eth_smii, spi0, spi1, spi2, spi3, sens0,
		sens1, uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0,
		i2s1, pcm1, pcm0, ks, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5,
		p0, sd0, sd1, sd2, i2c0, i2c1, i2c3, dsi, lvds, usb30, clko_25m,
		mipi_csi, nand, spdif, ts, lcd0]

		required:
		- groups
		- function

		additionalProperties: false

		'^(.*-)?pinconf$':
		type: object
		description:
		Pinctrl node's client devices specify pin configurations using
		subnodes, which in turn use the standard properties below.
		$ref: pincfg-node.yaml#

		properties:
		groups:
		description:
		List of gpio pin groups affected by the drive-strength property
		specified in this subnode.
		items:
		oneOf:
		- enum: [sirq_drv, rmii_txd01_txen_drv, rmii_rxer_drv,
		rmii_crs_drv, rmii_rxd10_drv, rmii_ref_clk_drv,
		smi_mdc_mdio_drv, i2s_d0_drv, i2s_bclk0_drv, i2s3_drv,
		i2s13_drv, pcm1_drv, ks_in_drv, ks_out_drv, lvds_all_drv,
		lcd_dsi_drv, dsi_drv, sd0_d0_d3_drv, sd1_d0_d3_drv,
		sd0_cmd_drv, sd0_clk_drv, sd1_cmd_drv, sd1_clk_drv,
		spi0_all_drv, uart0_rx_drv, uart0_tx_drv, uart2_all_drv,
		i2c0_all_drv, i2c12_all_drv, sens0_pclk_drv,
		sens0_ckout_drv, uart3_all_drv]
		minItems: 1
		maxItems: 32

		pins:
		description:
		List of gpio pins affected by the bias-pull-* and
		input-schmitt-* properties specified in this subnode.
		items:
		oneOf:
		- enum: [dnand_dqs, dnand_dqsn, eth_txd0, eth_txd1, eth_txen,
		eth_rxer, eth_crs_dv, eth_rxd1, eth_rxd0, eth_ref_clk,
		eth_mdc, eth_mdio, sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0,
		i2s_lrclk0, i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1,
		i2s_mclk1, ks_in0, ks_in1, ks_in2, ks_in3, ks_out0, ks_out1,
		ks_out2, lvds_oep, lvds_oen, lvds_odp, lvds_odn, lvds_ocp,
		lvds_ocn, lvds_obp, lvds_obn, lvds_oap, lvds_oan, lvds_eep,
		lvds_een, lvds_edp, lvds_edn, lvds_ecp, lvds_ecn, lvds_ebp,
		lvds_ebn, lvds_eap, lvds_ean, lcd0_d18, lcd0_d17, dsi_dp3,
		dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp, dsi_cn, dsi_dp0, dsi_dn0,
		dsi_dp2, dsi_dn2, sd0_d0, sd0_d1, sd0_d2, sd0_d3, sd1_d0,
		sd1_d1, sd1_d2, sd1_d3, sd0_cmd, sd0_clk, sd1_cmd, sd1_clk,
		spi0_sclk, spi0_ss, spi0_miso, spi0_mosi, uart0_rx,
		uart0_tx, i2c0_sclk, i2c0_sdata, sensor0_pclk,
		sensor0_ckout, dnand_ale, dnand_cle, dnand_ceb0, dnand_ceb1,
		dnand_ceb2, dnand_ceb3, uart2_rx, uart2_tx, uart2_rtsb,
		uart2_ctsb, uart3_rx, uart3_tx, uart3_rtsb, uart3_ctsb,
		pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, i2c1_sclk,
		i2c1_sdata, i2c2_sclk, i2c2_sdata, csi_dn0, csi_dp0,
		csi_dn1, csi_dp1, csi_dn2, csi_dp2, csi_dn3, csi_dp3,
		csi_cn, csi_cp, dnand_d0, dnand_d1, dnand_d2, dnand_d3,
		dnand_d4, dnand_d5, dnand_d6, dnand_d7, dnand_rb, dnand_rdb,
		dnand_rdbn, dnand_wrb, porb, clko_25m, bsel, pkg0, pkg1,
		pkg2, pkg3]
		minItems: 1
		maxItems: 64

		bias-pull-up: true
		bias-pull-down: true

		drive-strength:
		description:
		Selects the drive strength for the specified pins, in mA.
		enum: [2, 4, 8, 12]

		input-schmitt-enable: true
		input-schmitt-disable: true

		additionalProperties: false

		additionalProperties: false

		required:
		- compatible
		- reg
		- clocks
		- gpio-controller
		- gpio-ranges
		- '#gpio-cells'
		- interrupt-controller
		- '#interrupt-cells'
		- interrupts

		additionalProperties: false

		examples:
		- \|
		#include <dt-bindings/interrupt-controller/arm-gic.h>
		pinctrl: pinctrl@b01b0000 {
		compatible = "actions,s500-pinctrl";
		reg = <0xb01b0000 0x40>, <0xb01b0040 0x10>,
		<0xb01b0060 0x18>, <0xb01b0080 0xc>;
		clocks = <&cmu 55>;
		gpio-controller;
		gpio-ranges = <&pinctrl 0 0 132>;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;

		mmc0_pins: mmc0-pins {
		pinmux {
		groups = "sd0_d0_mfp", "sd0_d1_mfp", "sd0_d2_d3_mfp",
		"sd0_cmd_mfp", "sd0_clk_mfp";
		function = "sd0";
		};

		drv-pinconf {
		groups = "sd0_d0_d3_drv", "sd0_cmd_drv", "sd0_clk_drv";
		drive-strength = <8>;
		};

		bias-pinconf {
		pins = "sd0_d0", "sd0_d1", "sd0_d2",
		"sd0_d3", "sd0_cmd";
		bias-pull-up;
		};
		};
		};

		...

Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml

+84 −57

Original line number	Diff line number	Diff line
		@@ -48,6 +48,8 @@ properties:
		- allwinner,sun9i-a80-r-pinctrl
		- allwinner,sun50i-a64-pinctrl
		- allwinner,sun50i-a64-r-pinctrl
		- allwinner,sun50i-a100-pinctrl
		- allwinner,sun50i-a100-r-pinctrl
		- allwinner,sun50i-h5-pinctrl
		- allwinner,sun50i-h6-pinctrl
		- allwinner,sun50i-h6-r-pinctrl
		@@ -59,7 +61,7 @@ properties:

		interrupts:
		minItems: 1
		maxItems: 5
		maxItems: 7
		description:
		One interrupt per external interrupt bank supported on the
		controller, sorted by bank number ascending order.
		@@ -143,6 +145,18 @@ allOf:
		# boards are defining it at the moment so it would generate a lot of
		# warnings.

		- if:
		properties:
		compatible:
		enum:
		- allwinner,sun50i-a100-pinctrl

		then:
		properties:
		interrupts:
		minItems: 7
		maxItems: 7

		- if:
		properties:
		compatible:
		@@ -155,8 +169,7 @@ allOf:
		minItems: 5
		maxItems: 5

		else:
		if:
		- if:
		properties:
		compatible:
		enum:
		@@ -170,8 +183,7 @@ allOf:
		minItems: 4
		maxItems: 4

		else:
		if:
		- if:
		properties:
		compatible:
		enum:
		@@ -187,8 +199,7 @@ allOf:
		minItems: 3
		maxItems: 3

		else:
		if:
		- if:
		properties:
		compatible:
		enum:
		@@ -206,7 +217,23 @@ allOf:
		minItems: 2
		maxItems: 2

		else:
		- if:
		properties:
		compatible:
		enum:
		- allwinner,sun4i-a10-pinctrl
		- allwinner,sun5i-a10s-pinctrl
		- allwinner,sun5i-a13-pinctrl
		- allwinner,sun7i-a20-pinctrl
		- allwinner,sun8i-a23-r-pinctrl
		- allwinner,sun8i-a83t-r-pinctrl
		- allwinner,sun8i-h3-r-pinctrl
		- allwinner,sun8i-r40-pinctrl
		- allwinner,sun50i-a64-r-pinctrl
		- allwinner,sun50i-a100-r-pinctrl
		- nextthing,gr8-pinctrl

		then:
		properties:
		interrupts:
		minItems: 1

Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt

+3 −1

Original line number	Diff line number	Diff line
		@@ -4,7 +4,9 @@ The Atmel PIO4 controller is used to select the function of a pin and to
		configure it.

		Required properties:
		- compatible: "atmel,sama5d2-pinctrl".
		- compatible:
		"atmel,sama5d2-pinctrl"
		"microchip,sama7g5-pinctrl"
		- reg: base address and length of the PIO controller.
		- interrupts: interrupt outputs from the controller, one for each bank.
		- interrupt-controller: mark the device node as an interrupt controller.

Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt

+1 −0

Original line number	Diff line number	Diff line
		@@ -10,6 +10,7 @@ Required properties:
		"mediatek,mt7623-pinctrl", compatible with mt7623 pinctrl.
		"mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl.
		"mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
		"mediatek,mt8167-pinctrl", compatible with mt8167 pinctrl.
		"mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl.
		"mediatek,mt8516-pinctrl", compatible with mt8516 pinctrl.
		- pins-are-numbered: Specify the subnodes are using numbered pinmux to

Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml

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+155 −0

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		# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
		%YAML 1.2
		---
		$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8192.yaml#
		$schema: http://devicetree.org/meta-schemas/core.yaml#

		title: Mediatek MT8192 Pin Controller

		maintainers:
		- Sean Wang <sean.wang@mediatek.com>

		description: \|
		The Mediatek's Pin controller is used to control SoC pins.

		properties:
		compatible:
		const: mediatek,mt8192-pinctrl

		gpio-controller: true

		'#gpio-cells':
		description: \|
		Number of cells in GPIO specifier. Since the generic GPIO binding is used,
		the amount of cells must be specified as 2. See the below
		mentioned gpio binding representation for description of particular cells.
		const: 2

		gpio-ranges:
		description: gpio valid number range.
		maxItems: 1

		reg:
		description: \|
		Physical address base for gpio base registers. There are 11 GPIO
		physical address base in mt8192.
		maxItems: 11

		reg-names:
		description: \|
		Gpio base register names.
		maxItems: 11

		interrupt-controller: true

		'#interrupt-cells':
		const: 2

		interrupts:
		description: The interrupt outputs to sysirq.
		maxItems: 1

		#PIN CONFIGURATION NODES
		patternProperties:
		'^pins':
		type: object
		description: \|
		A pinctrl node should contain at least one subnodes representing the
		pinctrl groups available on the machine. Each subnode will list the
		pins it needs, and how they should be configured, with regard to muxer
		configuration, pullups, drive strength, input enable/disable and
		input schmitt.
		An example of using macro:
		pincontroller {
		/* GPIO0 set as multifunction GPIO0 */
		state_0_node_a {
		pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
		};
		/* GPIO1 set as multifunction PWM */
		state_0_node_b {
		pinmux = <PINMUX_GPIO1__FUNC_PWM_1>;
		};
		};
		$ref: "pinmux-node.yaml"

		properties:
		pinmux:
		description: \|
		Integer array, represents gpio pin number and mux setting.
		Supported pin number and mux varies for different SoCs, and are defined
		as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.

		drive-strength:
		description: \|
		It can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See
		dt-bindings/pinctrl/mt65xx.h. It can only support 2/4/6/8/10/12/14/16mA in mt8192.
		enum: [2, 4, 6, 8, 10, 12, 14, 16]

		bias-pull-down: true

		bias-pull-up: true

		bias-disable: true

		output-high: true

		output-low: true

		input-enable: true

		input-disable: true

		input-schmitt-enable: true

		input-schmitt-disable: true

		required:
		- pinmux

		additionalProperties: false

		required:
		- compatible
		- reg
		- interrupts
		- interrupt-controller
		- '#interrupt-cells'
		- gpio-controller
		- '#gpio-cells'
		- gpio-ranges

		additionalProperties: false

		examples:
		- \|
		#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
		#include <dt-bindings/interrupt-controller/arm-gic.h>
		pio: pinctrl@10005000 {
		compatible = "mediatek,mt8192-pinctrl";
		reg = <0x10005000 0x1000>,
		<0x11c20000 0x1000>,
		<0x11d10000 0x1000>,
		<0x11d30000 0x1000>,
		<0x11d40000 0x1000>,
		<0x11e20000 0x1000>,
		<0x11e70000 0x1000>,
		<0x11ea0000 0x1000>,
		<0x11f20000 0x1000>,
		<0x11f30000 0x1000>,
		<0x1000b000 0x1000>;
		reg-names = "iocfg0", "iocfg_rm", "iocfg_bm",
		"iocfg_bl", "iocfg_br", "iocfg_lm",
		"iocfg_lb", "iocfg_rt", "iocfg_lt",
		"iocfg_tl", "eint";
		gpio-controller;
		#gpio-cells = <2>;
		gpio-ranges = <&pio 0 0 220>;
		interrupt-controller;
		interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>;
		#interrupt-cells = <2>;

		pins {
		pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
		output-low;
		};
		};

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