arm64: dts: qcom: qcs404: add base dts files

// SPDX-License-Identifier: GPL-2.0

// Copyright (c) 2018, Linaro Limited

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/clock/qcom,gcc-qcs404.h>

/ {

	interrupt-parent = <&intc>;

	#address-cells = <2>;

	#size-cells = <2>;

	chosen { };

	clocks {

		xo_board: xo-board {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <19200000>;

		};

	};

	cpus {

		#address-cells = <1>;

		#size-cells = <0>;

		CPU0: cpu@100 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x100>;

			enable-method = "psci";

			next-level-cache = <&L2_0>;

		};

		CPU1: cpu@101 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x101>;

			enable-method = "psci";

			next-level-cache = <&L2_0>;

		};

		CPU2: cpu@102 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x102>;

			enable-method = "psci";

			next-level-cache = <&L2_0>;

		};

		CPU3: cpu@103 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x103>;

			enable-method = "psci";

			next-level-cache = <&L2_0>;

		};

		L2_0: l2-cache {

			compatible = "cache";

			cache-level = <2>;

		};

	};

	memory@80000000 {

		device_type = "memory";

		/* We expect the bootloader to fill in the size */

		reg = <0 0x80000000 0 0>;

	};

	psci {

		compatible = "arm,psci-1.0";

		method = "smc";

	};

	soc: soc@0 {

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0 0 0 0xffffffff>;

		compatible = "simple-bus";

		gcc: clock-controller@1800000 {

			compatible = "qcom,gcc-qcs404";

			reg = <0x01800000 0x80000>;

			#clock-cells = <1>;

			assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>;

			assigned-clock-rates = <19200000>;

		};

		blsp1_uart2: serial@78b1000 {

			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";

			reg = <0x078b1000 0x200>;

			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			status = "okay";

		};

		intc: interrupt-controller@b000000 {

			compatible = "qcom,msm-qgic2";

			interrupt-controller;

			#interrupt-cells = <3>;

			reg = <0x0b000000 0x1000>,

			      <0x0b002000 0x1000>;

		};

		timer@b120000 {

			#address-cells = <1>;

			#size-cells = <1>;

			ranges;

			compatible = "arm,armv7-timer-mem";

			reg = <0x0b120000 0x1000>;

			clock-frequency = <19200000>;

			frame@b121000 {

				frame-number = <0>;

				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x0b121000 0x1000>,

				      <0x0b122000 0x1000>;

			};

			frame@b123000 {

				frame-number = <1>;

				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x0b123000 0x1000>;

				status = "disabled";

			};

			frame@b124000 {

				frame-number = <2>;

				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x0b124000 0x1000>;

				status = "disabled";

			};

			frame@b125000 {

				frame-number = <3>;

				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x0b125000 0x1000>;

				status = "disabled";

			};

			frame@b126000 {

				frame-number = <4>;

				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x0b126000 0x1000>;

				status = "disabled";

			};

			frame@b127000 {

				frame-number = <5>;

				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0xb127000 0x1000>;

				status = "disabled";

			};

			frame@b128000 {

				frame-number = <6>;

				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x0b128000 0x1000>;

				status = "disabled";

			};

		};

	};

	timer {

		compatible = "arm,armv8-timer";

		interrupts = <GIC_PPI 2 0xff08>,

			     <GIC_PPI 3 0xff08>,

			     <GIC_PPI 4 0xff08>,

			     <GIC_PPI 1 0xff08>;

	};

};