Commit b4d3acaa authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915/gt: Pull sseu context updates under gt 



Lift the routines to emit a request to update the SSEU on the
intel_context out of i915_gem_context.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarMatthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200131104548.2451485-6-chris@chris-wilson.co.uk
parent 0a3b94a2

drivers/gpu/drm/i915/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -81,6 +81,7 @@ gt-y += \ 
	gt/gen8_ppgtt.o \

	gt/intel_breadcrumbs.o \

	gt/intel_context.o \

	gt/intel_context_sseu.o \

	gt/intel_engine_cs.o \

	gt/intel_engine_heartbeat.o \

	gt/intel_engine_pm.o \

drivers/gpu/drm/i915/gem/i915_gem_context.c

+0 −85
Original line number Diff line number Diff line
@@ -72,9 +72,7 @@ 
#include "gt/gen6_ppgtt.h"

#include "gt/intel_context.h"

#include "gt/intel_engine_heartbeat.h"

#include "gt/intel_engine_pm.h"

#include "gt/intel_engine_user.h"

#include "gt/intel_lrc_reg.h"

#include "gt/intel_ring.h"



#include "i915_gem_context.h"
@@ -1184,89 +1182,6 @@ out: 
	return err;

}



static int gen8_emit_rpcs_config(struct i915_request *rq,

				 struct intel_context *ce,

				 struct intel_sseu sseu)

{

	u64 offset;

	u32 *cs;



	cs = intel_ring_begin(rq, 4);

	if (IS_ERR(cs))

		return PTR_ERR(cs);



	offset = i915_ggtt_offset(ce->state) +

		 LRC_STATE_PN * PAGE_SIZE +

		 CTX_R_PWR_CLK_STATE * 4;



	*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;

	*cs++ = lower_32_bits(offset);

	*cs++ = upper_32_bits(offset);

	*cs++ = intel_sseu_make_rpcs(rq->i915, &sseu);



	intel_ring_advance(rq, cs);



	return 0;

}



static int

gen8_modify_rpcs(struct intel_context *ce, struct intel_sseu sseu)

{

	struct i915_request *rq;

	int ret;



	lockdep_assert_held(&ce->pin_mutex);



	/*

	 * If the context is not idle, we have to submit an ordered request to

	 * modify its context image via the kernel context (writing to our own

	 * image, or into the registers directory, does not stick). Pristine

	 * and idle contexts will be configured on pinning.

	 */

	if (!intel_context_pin_if_active(ce))

		return 0;



	rq = intel_engine_create_kernel_request(ce->engine);

	if (IS_ERR(rq)) {

		ret = PTR_ERR(rq);

		goto out_unpin;

	}



	/* Serialise with the remote context */

	ret = intel_context_prepare_remote_request(ce, rq);

	if (ret == 0)

		ret = gen8_emit_rpcs_config(rq, ce, sseu);



	i915_request_add(rq);

out_unpin:

	intel_context_unpin(ce);

	return ret;

}



static int

intel_context_reconfigure_sseu(struct intel_context *ce, struct intel_sseu sseu)

{

	int ret;



	GEM_BUG_ON(INTEL_GEN(ce->engine->i915) < 8);



	ret = intel_context_lock_pinned(ce);

	if (ret)

		return ret;



	/* Nothing to do if unmodified. */

	if (!memcmp(&ce->sseu, &sseu, sizeof(sseu)))

		goto unlock;



	ret = gen8_modify_rpcs(ce, sseu);

	if (!ret)

		ce->sseu = sseu;



unlock:

	intel_context_unlock_pinned(ce);

	return ret;

}



static int

user_to_context_sseu(struct drm_i915_private *i915,

		     const struct drm_i915_gem_context_param_sseu *user,

drivers/gpu/drm/i915/gt/intel_context.h

+3 −0
Original line number Diff line number Diff line
@@ -35,6 +35,9 @@ int intel_context_alloc_state(struct intel_context *ce); 


void intel_context_free(struct intel_context *ce);



int intel_context_reconfigure_sseu(struct intel_context *ce,

				   const struct intel_sseu sseu);



/**

 * intel_context_lock_pinned - Stablises the 'pinned' status of the HW context

 * @ce - the context

drivers/gpu/drm/i915/gt/intel_context_sseu.c

0 → 100644
+98 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: MIT

/*

 * Copyright © 2019 Intel Corporation

 */



#include "i915_drv.h"

#include "i915_vma.h"

#include "intel_context.h"

#include "intel_engine_pm.h"

#include "intel_gpu_commands.h"

#include "intel_lrc.h"

#include "intel_lrc_reg.h"

#include "intel_ring.h"

#include "intel_sseu.h"



static int gen8_emit_rpcs_config(struct i915_request *rq,

				 const struct intel_context *ce,

				 const struct intel_sseu sseu)

{

	u64 offset;

	u32 *cs;



	cs = intel_ring_begin(rq, 4);

	if (IS_ERR(cs))

		return PTR_ERR(cs);



	offset = i915_ggtt_offset(ce->state) +

		 LRC_STATE_PN * PAGE_SIZE +

		 CTX_R_PWR_CLK_STATE * 4;



	*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;

	*cs++ = lower_32_bits(offset);

	*cs++ = upper_32_bits(offset);

	*cs++ = intel_sseu_make_rpcs(rq->i915, &sseu);



	intel_ring_advance(rq, cs);



	return 0;

}



static int

gen8_modify_rpcs(struct intel_context *ce, const struct intel_sseu sseu)

{

	struct i915_request *rq;

	int ret;



	lockdep_assert_held(&ce->pin_mutex);



	/*

	 * If the context is not idle, we have to submit an ordered request to

	 * modify its context image via the kernel context (writing to our own

	 * image, or into the registers directory, does not stick). Pristine

	 * and idle contexts will be configured on pinning.

	 */

	if (!intel_context_pin_if_active(ce))

		return 0;



	rq = intel_engine_create_kernel_request(ce->engine);

	if (IS_ERR(rq)) {

		ret = PTR_ERR(rq);

		goto out_unpin;

	}



	/* Serialise with the remote context */

	ret = intel_context_prepare_remote_request(ce, rq);

	if (ret == 0)

		ret = gen8_emit_rpcs_config(rq, ce, sseu);



	i915_request_add(rq);

out_unpin:

	intel_context_unpin(ce);

	return ret;

}



int

intel_context_reconfigure_sseu(struct intel_context *ce,

			       const struct intel_sseu sseu)

{

	int ret;



	GEM_BUG_ON(INTEL_GEN(ce->engine->i915) < 8);



	ret = intel_context_lock_pinned(ce);

	if (ret)

		return ret;



	/* Nothing to do if unmodified. */

	if (!memcmp(&ce->sseu, &sseu, sizeof(sseu)))

		goto unlock;



	ret = gen8_modify_rpcs(ce, sseu);

	if (!ret)

		ce->sseu = sseu;



unlock:

	intel_context_unlock_pinned(ce);

	return ret;

}

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