Commit b4beb4bf authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'for-linus/i2c-3.2' of git://git.fluff.org/bjdooks/linux 

* 'for-linus/i2c-3.2' of git://git.fluff.org/bjdooks/linux: (47 commits)
  i2c-s3c2410: Add device tree support
  i2c-s3c2410: Keep a copy of platform data and use it
  i2c-nomadik: cosmetic coding style corrections
  i2c-au1550: dev_pm_ops conversion
  i2c-au1550: increase timeout waiting for master done
  i2c-au1550: remove unused ack_timeout
  i2c-au1550: remove usage of volatile keyword
  i2c-tegra: __iomem annotation fix
  i2c-eg20t: Add initialize processing in case i2c-error occurs
  i2c-eg20t: Fix flag setting issue
  i2c-eg20t: add stop sequence in case wait-event timeout occurs
  i2c-eg20t: Separate error processing
  i2c-eg20t: Fix 10bit access issue
  i2c-eg20t: Modify returned value s32 to long
  i2c-eg20t: Fix bus-idle waiting issue
  i2c-designware: Fix PCI core warning on suspend/resume
  i2c-designware: Add runtime power management support
  i2c-designware: Add support for Designware core behind PCI devices.
  i2c-designware: Push all register reads/writes into the core code.
  i2c-designware: Support multiple cores using same ISR
  ...
parents f3c3f067 3945fe93

Documentation/devicetree/bindings/i2c/fsl-imx-i2c.txt

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+25 −0
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* Freescale Inter IC (I2C) and High Speed Inter IC (HS-I2C) for i.MX



Required properties:

- compatible : Should be "fsl,<chip>-i2c"

- reg : Should contain I2C/HS-I2C registers location and length

- interrupts : Should contain I2C/HS-I2C interrupt



Optional properties:

- clock-frequency : Constains desired I2C/HS-I2C bus clock frequency in Hz.

  The absence of the propoerty indicates the default frequency 100 kHz.



Examples:



i2c@83fc4000 { /* I2C2 on i.MX51 */

	compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";

	reg = <0x83fc4000 0x4000>;

	interrupts = <63>;

};



i2c@70038000 { /* HS-I2C on i.MX51 */

	compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";

	reg = <0x70038000 0x4000>;

	interrupts = <64>;

	clock-frequency = <400000>;

};

Documentation/devicetree/bindings/i2c/samsung-i2c.txt

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* Samsung's I2C controller



The Samsung's I2C controller is used to interface with I2C devices.



Required properties:

  - compatible: value should be either of the following.

      (a) "samsung, s3c2410-i2c", for i2c compatible with s3c2410 i2c.

      (b) "samsung, s3c2440-i2c", for i2c compatible with s3c2440 i2c.

  - reg: physical base address of the controller and length of memory mapped

    region.

  - interrupts: interrupt number to the cpu.

  - samsung,i2c-sda-delay: Delay (in ns) applied to data line (SDA) edges.

  - gpios: The order of the gpios should be the following: <SDA, SCL>.

    The gpio specifier depends on the gpio controller.



Optional properties:

  - samsung,i2c-slave-addr: Slave address in multi-master enviroment. If not

    specified, default value is 0.

  - samsung,i2c-max-bus-freq: Desired frequency in Hz of the bus. If not

    specified, the default value in Hz is 100000.



Example:



	i2c@13870000 {

		compatible = "samsung,s3c2440-i2c";

		reg = <0x13870000 0x100>;

		interrupts = <345>;

		samsung,i2c-sda-delay = <100>;

		samsung,i2c-max-bus-freq = <100000>;

		gpios = <&gpd1 2 0 /* SDA */

			 &gpd1 3 0 /* SCL */>;

		#address-cells = <1>;

		#size-cells = <0>;



		wm8994@1a {

			compatible = "wlf,wm8994";

			reg = <0x1a>;

		};

	};

arch/arm/plat-mxc/include/mach/i2c.h

+0 −4
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@@ -11,14 +11,10 @@ 


/**

 * struct imxi2c_platform_data - structure of platform data for MXC I2C driver

 * @init:	Initialise gpio's and other board specific things

 * @exit:	Free everything initialised by @init

 * @bitrate:	Bus speed measured in Hz

 *

 **/

struct imxi2c_platform_data {

	int (*init)(struct device *dev);

	void (*exit)(struct device *dev);

	int bitrate;

};

arch/arm/plat-omap/i2c.c

+27 −0
Original line number Diff line number Diff line
@@ -108,6 +108,22 @@ static inline int omap1_i2c_add_bus(int bus_id) 
	res[1].start = INT_I2C;

	pdata = &i2c_pdata[bus_id - 1];



	/* all OMAP1 have IP version 1 register set */

	pdata->rev = OMAP_I2C_IP_VERSION_1;



	/* all OMAP1 I2C are implemented like this */

	pdata->flags = OMAP_I2C_FLAG_NO_FIFO |

		       OMAP_I2C_FLAG_SIMPLE_CLOCK |

		       OMAP_I2C_FLAG_16BIT_DATA_REG |

		       OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK;



	/* how the cpu bus is wired up differs for 7xx only */



	if (cpu_is_omap7xx())

		pdata->flags |= OMAP_I2C_FLAG_BUS_SHIFT_1;

	else

		pdata->flags |= OMAP_I2C_FLAG_BUS_SHIFT_2;



	return platform_device_register(pdev);

}
@@ -138,6 +154,7 @@ static inline int omap2_i2c_add_bus(int bus_id) 
	struct omap_device *od;

	char oh_name[MAX_OMAP_I2C_HWMOD_NAME_LEN];

	struct omap_i2c_bus_platform_data *pdata;

	struct omap_i2c_dev_attr *dev_attr;



	omap2_i2c_mux_pins(bus_id);
@@ -151,6 +168,16 @@ static inline int omap2_i2c_add_bus(int bus_id) 
	}



	pdata = &i2c_pdata[bus_id - 1];

	/*

	 * pass the hwmod class's CPU-specific knowledge of I2C IP revision in

	 * use, and functionality implementation flags, up to the OMAP I2C

	 * driver via platform data

	 */

	pdata->rev = oh->class->rev;



	dev_attr = (struct omap_i2c_dev_attr *)oh->dev_attr;

	pdata->flags = dev_attr->flags;



	/*

	 * When waiting for completion of a i2c transfer, we need to

	 * set a wake up latency constraint for the MPU. This is to

arch/mips/include/asm/mach-au1x00/au1xxx_psc.h

+0 −13
Original line number Diff line number Diff line
@@ -394,19 +394,6 @@ typedef struct psc_spi { 
#define PSC_SPITXRX_LC		(1 << 29)

#define PSC_SPITXRX_SR		(1 << 28)



/* PSC in SMBus (I2C) Mode. */

typedef struct	psc_smb {

	u32	psc_sel;

	u32	psc_ctrl;

	u32	psc_smbcfg;

	u32	psc_smbmsk;

	u32	psc_smbpcr;

	u32	psc_smbstat;

	u32	psc_smbevnt;

	u32	psc_smbtxrx;

	u32	psc_smbtmr;

} psc_smb_t;



/* SMBus Config Register. */

#define PSC_SMBCFG_RT_MASK	(3 << 30)

#define PSC_SMBCFG_RT_FIFO1	(0 << 30)

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