Commit b4ba1f0f authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux 

Pull arm64 fixes from Catalin Marinas:

 - Fix size alignment in __iommu_{alloc,free}_attrs

 - Kernel memory mapping fix with CONFIG_DEBUG_RODATA for page sizes
   other than 4KB and a fix of the mark_rodata_ro permissions

 - dma_get_ops() simplification and behaviour alignment between DT and
   ACPI

 - function_graph trace fix for cpu_suspend() (CPUs returning from deep
   sleep via a different path and confusing the tracer)

 - Use of non-global mappings for UEFI run-time services to avoid a
   (potentially theoretical) TLB conflict

 - Crypto priority reduction of core AES cipher (the accelerated
   asynchronous implementation is preferred when available)

 - Reverting an old commit that removed BogoMIPS from /proc/cpuinfo on
   arm64.  Apparently, we had it for a relatively short time and libvirt
   started checking for its presence

 - Compiler warnings fixed (ptrace.h inclusion from compat.h,
   smp_load_acquire with const argument)

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64: restore bogomips information in /proc/cpuinfo
  arm64: barriers: fix smp_load_acquire to work with const arguments
  arm64: Fix R/O permissions in mark_rodata_ro
  arm64: crypto: reduce priority of core AES cipher
  arm64: use non-global mappings for UEFI runtime regions
  arm64: kernel: pause/unpause function graph tracer in cpu_suspend()
  arm64: do not include ptrace.h from compat.h
  arm64: simplify dma_get_ops
  arm64: mm: use correct mapping granularity under DEBUG_RODATA
  arm64/dma-mapping: Fix sizes in __iommu_{alloc,free}_attrs
parents a3d66b5a 92e788b7

arch/arm64/crypto/aes-ce-cipher.c

+1 −1
Original line number Diff line number Diff line
@@ -237,7 +237,7 @@ EXPORT_SYMBOL(ce_aes_setkey); 
static struct crypto_alg aes_alg = {

	.cra_name		= "aes",

	.cra_driver_name	= "aes-ce",

	.cra_priority		= 300,

	.cra_priority		= 250,

	.cra_flags		= CRYPTO_ALG_TYPE_CIPHER,

	.cra_blocksize		= AES_BLOCK_SIZE,

	.cra_ctxsize		= sizeof(struct crypto_aes_ctx),

arch/arm64/include/asm/barrier.h

+10 −6
Original line number Diff line number Diff line
@@ -64,27 +64,31 @@ do { \ 


#define smp_load_acquire(p)						\

({									\

	typeof(*p) ___p1;						\

	union { typeof(*p) __val; char __c[1]; } __u;			\

	compiletime_assert_atomic_type(*p);				\

	switch (sizeof(*p)) {						\

	case 1:								\

		asm volatile ("ldarb %w0, %1"				\

			: "=r" (___p1) : "Q" (*p) : "memory");		\

			: "=r" (*(__u8 *)__u.__c)			\

			: "Q" (*p) : "memory");				\

		break;							\

	case 2:								\

		asm volatile ("ldarh %w0, %1"				\

			: "=r" (___p1) : "Q" (*p) : "memory");		\

			: "=r" (*(__u16 *)__u.__c)			\

			: "Q" (*p) : "memory");				\

		break;							\

	case 4:								\

		asm volatile ("ldar %w0, %1"				\

			: "=r" (___p1) : "Q" (*p) : "memory");		\

			: "=r" (*(__u32 *)__u.__c)			\

			: "Q" (*p) : "memory");				\

		break;							\

	case 8:								\

		asm volatile ("ldar %0, %1"				\

			: "=r" (___p1) : "Q" (*p) : "memory");		\

			: "=r" (*(__u64 *)__u.__c)			\

			: "Q" (*p) : "memory");				\

		break;							\

	}								\

	___p1;								\

	__u.__val;							\

})



#define read_barrier_depends()		do { } while(0)

arch/arm64/include/asm/compat.h

+1 −2
Original line number Diff line number Diff line
@@ -23,7 +23,6 @@ 
 */

#include <linux/types.h>

#include <linux/sched.h>

#include <linux/ptrace.h>



#define COMPAT_USER_HZ		100

#ifdef __AARCH64EB__
@@ -234,7 +233,7 @@ static inline compat_uptr_t ptr_to_compat(void __user *uptr) 
	return (u32)(unsigned long)uptr;

}



#define compat_user_stack_pointer() (user_stack_pointer(current_pt_regs()))

#define compat_user_stack_pointer() (user_stack_pointer(task_pt_regs(current)))



static inline void __user *arch_compat_alloc_user_space(long len)

{

arch/arm64/include/asm/dma-mapping.h

+3 −10
Original line number Diff line number Diff line
@@ -18,7 +18,6 @@ 


#ifdef __KERNEL__



#include <linux/acpi.h>

#include <linux/types.h>

#include <linux/vmalloc.h>
@@ -26,22 +25,16 @@ 
#include <asm/xen/hypervisor.h>



#define DMA_ERROR_CODE	(~(dma_addr_t)0)

extern struct dma_map_ops *dma_ops;

extern struct dma_map_ops dummy_dma_ops;



static inline struct dma_map_ops *__generic_dma_ops(struct device *dev)

{

	if (unlikely(!dev))

		return dma_ops;

	else if (dev->archdata.dma_ops)

	if (dev && dev->archdata.dma_ops)

		return dev->archdata.dma_ops;

	else if (acpi_disabled)

		return dma_ops;



	/*

	 * When ACPI is enabled, if arch_set_dma_ops is not called,

	 * we will disable device DMA capability by setting it

	 * to dummy_dma_ops.

	 * We expect no ISA devices, and all other DMA masters are expected to

	 * have someone call arch_setup_dma_ops at device creation time.

	 */

	return &dummy_dma_ops;

}

arch/arm64/include/asm/mmu_context.h

+1 −1
Original line number Diff line number Diff line
@@ -101,7 +101,7 @@ static inline void cpu_set_default_tcr_t0sz(void) 
#define destroy_context(mm)		do { } while(0)

void check_and_switch_context(struct mm_struct *mm, unsigned int cpu);



#define init_new_context(tsk,mm)	({ atomic64_set(&mm->context.id, 0); 0; })

#define init_new_context(tsk,mm)	({ atomic64_set(&(mm)->context.id, 0); 0; })



/*

 * This is called when "tsk" is about to enter lazy TLB mode.

CRA Git | Maintained and supported by SUSTech CRA and CCSE