net: mvpp2: check first level interrupt status registers

#define     MVPP22_CTRL4_DP_CLK_SEL		BIT(5)

#define     MVPP22_CTRL4_SYNC_BYPASS_DIS	BIT(6)

#define     MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE	BIT(7)

#define MVPP22_GMAC_INT_SUM_STAT		0xa0

#define	    MVPP22_GMAC_INT_SUM_STAT_INTERNAL	BIT(1)

#define MVPP22_GMAC_INT_SUM_MASK		0xa4

#define     MVPP22_GMAC_INT_SUM_MASK_LINK_STAT	BIT(1)

#define     MVPP22_XLG_CTRL3_MACMODESELECT_MASK	(7 << 13)

#define     MVPP22_XLG_CTRL3_MACMODESELECT_GMAC	(0 << 13)

#define     MVPP22_XLG_CTRL3_MACMODESELECT_10G	(1 << 13)

#define MVPP22_XLG_EXT_INT_STAT			0x158

#define     MVPP22_XLG_EXT_INT_STAT_XLG		BIT(1)

#define MVPP22_XLG_EXT_INT_MASK			0x15c

#define     MVPP22_XLG_EXT_INT_MASK_XLG		BIT(1)

#define     MVPP22_XLG_EXT_INT_MASK_GIG		BIT(2)

static irqreturn_t mvpp2_port_isr(int irq, void *dev_id)

{

	struct mvpp2_port *port = (struct mvpp2_port *)dev_id;

	u32 val;

	mvpp22_gop_mask_irq(port);

	if (mvpp2_port_supports_xlg(port) &&

	    mvpp2_is_xlg(port->phy_interface)) {

		/* Check the external status register */

		val = readl(port->base + MVPP22_XLG_EXT_INT_STAT);

		if (val & MVPP22_XLG_EXT_INT_STAT_XLG)

			mvpp2_isr_handle_xlg(port);

	} else {

		/* If it's not the XLG, we must be using the GMAC.

		 * Check the summary status.

		 */

		val = readl(port->base + MVPP22_GMAC_INT_SUM_STAT);

		if (val & MVPP22_GMAC_INT_SUM_STAT_INTERNAL)

			mvpp2_isr_handle_gmac_internal(port);

	}