Commit b4a4cb5a authored by Anson Huang's avatar Anson Huang Committed by Stephen Boyd
Browse files

clk: imx: correct i.MX7D AV PLL num/denom offset 



According reference manual, i.MX7D's audio/video PLL's
num/denom register offset are 0x20/0x30, they are different
from i.MX6's audio/video PLL, correct it by introducing new
offset variables for audio/video PLL and using runtime
assignment based on PLL type.

Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 6ff46d77

drivers/clk/imx/clk-imx7d.c

+2 −2
Original line number Diff line number Diff line
@@ -417,8 +417,8 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) 
	clks[IMX7D_PLL_DRAM_MAIN] = imx_clk_pllv3(IMX_PLLV3_DDR_IMX7, "pll_dram_main", "osc", base + 0x70, 0x7f);

	clks[IMX7D_PLL_SYS_MAIN]  = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll_sys_main", "osc", base + 0xb0, 0x1);

	clks[IMX7D_PLL_ENET_MAIN] = imx_clk_pllv3(IMX_PLLV3_ENET_IMX7, "pll_enet_main", "osc", base + 0xe0, 0x0);

	clks[IMX7D_PLL_AUDIO_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV, "pll_audio_main", "osc", base + 0xf0, 0x7f);

	clks[IMX7D_PLL_VIDEO_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV, "pll_video_main", "osc", base + 0x130, 0x7f);

	clks[IMX7D_PLL_AUDIO_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV_IMX7, "pll_audio_main", "osc", base + 0xf0, 0x7f);

	clks[IMX7D_PLL_VIDEO_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV_IMX7, "pll_video_main", "osc", base + 0x130, 0x7f);



	clks[IMX7D_PLL_ARM_MAIN_BYPASS]  = imx_clk_mux_flags("pll_arm_main_bypass", base + 0x60, 16, 1, pll_arm_bypass_sel, ARRAY_SIZE(pll_arm_bypass_sel), CLK_SET_RATE_PARENT);

	clks[IMX7D_PLL_DRAM_MAIN_BYPASS] = imx_clk_mux_flags("pll_dram_main_bypass", base + 0x70, 16, 1, pll_dram_bypass_sel, ARRAY_SIZE(pll_dram_bypass_sel), CLK_SET_RATE_PARENT);

drivers/clk/imx/clk-pllv3.c

+21 −8
Original line number Diff line number Diff line
@@ -20,6 +20,8 @@ 


#define PLL_NUM_OFFSET		0x10

#define PLL_DENOM_OFFSET	0x20

#define PLL_IMX7_NUM_OFFSET	0x20

#define PLL_IMX7_DENOM_OFFSET	0x30



#define PLL_VF610_NUM_OFFSET	0x20

#define PLL_VF610_DENOM_OFFSET	0x30
@@ -49,6 +51,8 @@ struct clk_pllv3 { 
	u32		div_mask;

	u32		div_shift;

	unsigned long	ref_clock;

	u32		num_offset;

	u32		denom_offset;

};



#define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
@@ -219,8 +223,8 @@ static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw, 
					      unsigned long parent_rate)

{

	struct clk_pllv3 *pll = to_clk_pllv3(hw);

	u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET);

	u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET);

	u32 mfn = readl_relaxed(pll->base + pll->num_offset);

	u32 mfd = readl_relaxed(pll->base + pll->denom_offset);

	u32 div = readl_relaxed(pll->base) & pll->div_mask;

	u64 temp64 = (u64)parent_rate;
@@ -289,8 +293,8 @@ static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate, 
	val &= ~pll->div_mask;

	val |= div;

	writel_relaxed(val, pll->base);

	writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);

	writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET);

	writel_relaxed(mfn, pll->base + pll->num_offset);

	writel_relaxed(mfd, pll->base + pll->denom_offset);



	return clk_pllv3_wait_lock(pll);

}
@@ -352,8 +356,8 @@ static unsigned long clk_pllv3_vf610_recalc_rate(struct clk_hw *hw, 
	struct clk_pllv3 *pll = to_clk_pllv3(hw);

	struct clk_pllv3_vf610_mf mf;



	mf.mfn = readl_relaxed(pll->base + PLL_VF610_NUM_OFFSET);

	mf.mfd = readl_relaxed(pll->base + PLL_VF610_DENOM_OFFSET);

	mf.mfn = readl_relaxed(pll->base + pll->num_offset);

	mf.mfd = readl_relaxed(pll->base + pll->denom_offset);

	mf.mfi = (readl_relaxed(pll->base) & pll->div_mask) ? 22 : 20;



	return clk_pllv3_vf610_mf_to_rate(parent_rate, mf);
@@ -382,8 +386,8 @@ static int clk_pllv3_vf610_set_rate(struct clk_hw *hw, unsigned long rate, 
		val |= pll->div_mask;	/* set bit for mfi=22 */

	writel_relaxed(val, pll->base);



	writel_relaxed(mf.mfn, pll->base + PLL_VF610_NUM_OFFSET);

	writel_relaxed(mf.mfd, pll->base + PLL_VF610_DENOM_OFFSET);

	writel_relaxed(mf.mfn, pll->base + pll->num_offset);

	writel_relaxed(mf.mfd, pll->base + pll->denom_offset);



	return clk_pllv3_wait_lock(pll);

}
@@ -426,6 +430,8 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, 
		return ERR_PTR(-ENOMEM);



	pll->power_bit = BM_PLL_POWER;

	pll->num_offset = PLL_NUM_OFFSET;

	pll->denom_offset = PLL_DENOM_OFFSET;



	switch (type) {

	case IMX_PLLV3_SYS:
@@ -433,6 +439,8 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, 
		break;

	case IMX_PLLV3_SYS_VF610:

		ops = &clk_pllv3_vf610_ops;

		pll->num_offset = PLL_VF610_NUM_OFFSET;

		pll->denom_offset = PLL_VF610_DENOM_OFFSET;

		break;

	case IMX_PLLV3_USB_VF610:

		pll->div_shift = 1;
@@ -440,6 +448,9 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, 
		ops = &clk_pllv3_ops;

		pll->powerup_set = true;

		break;

	case IMX_PLLV3_AV_IMX7:

		pll->num_offset = PLL_IMX7_NUM_OFFSET;

		pll->denom_offset = PLL_IMX7_DENOM_OFFSET;

	case IMX_PLLV3_AV:

		ops = &clk_pllv3_av_ops;

		break;
@@ -454,6 +465,8 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, 
		break;

	case IMX_PLLV3_DDR_IMX7:

		pll->power_bit = IMX7_DDR_PLL_POWER;

		pll->num_offset = PLL_IMX7_NUM_OFFSET;

		pll->denom_offset = PLL_IMX7_DENOM_OFFSET;

		ops = &clk_pllv3_av_ops;

		break;

	default:

drivers/clk/imx/clk.h

+1 −0
Original line number Diff line number Diff line
@@ -77,6 +77,7 @@ enum imx_pllv3_type { 
	IMX_PLLV3_ENET_IMX7,

	IMX_PLLV3_SYS_VF610,

	IMX_PLLV3_DDR_IMX7,

	IMX_PLLV3_AV_IMX7,

};



struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,

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