Commit b4a4bd0f authored by Marc Zyngier's avatar Marc Zyngier
Browse files

irqchip/gic-v4.1: Add VPE INVALL callback 



GICv4.1 redistributors have a VPE-aware INVALL register. Progress!
We can now emulate a guest-requested INVALL without emiting a
VINVALL command.

Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Reviewed-by: default avatarZenghui Yu <yuzenghui@huawei.com>
Link: https://lore.kernel.org/r/20191224111055.11836-14-maz@kernel.org
parent e64fab1a

drivers/irqchip/irq-gic-v3-its.c

+14 −0
Original line number Diff line number Diff line
@@ -3669,6 +3669,19 @@ static void its_vpe_4_1_deschedule(struct its_vpe *vpe, 
	}

}



static void its_vpe_4_1_invall(struct its_vpe *vpe)

{

	void __iomem *rdbase;

	u64 val;



	val  = GICR_INVALLR_V;

	val |= FIELD_PREP(GICR_INVALLR_VPEID, vpe->vpe_id);



	/* Target the redistributor this vPE is currently known on */

	rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;

	gic_write_lpir(val, rdbase + GICR_INVALLR);

}



static int its_vpe_4_1_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)

{

	struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
@@ -3684,6 +3697,7 @@ static int its_vpe_4_1_set_vcpu_affinity(struct irq_data *d, void *vcpu_info) 
		return 0;



	case INVALL_VPE:

		its_vpe_4_1_invall(vpe);

		return 0;



	default:

include/linux/irqchip/arm-gic-v3.h

+6 −0
Original line number Diff line number Diff line
@@ -247,6 +247,12 @@ 
#define GICR_TYPER_COMMON_LPI_AFF	GENMASK_ULL(25, 24)

#define GICR_TYPER_AFFINITY		GENMASK_ULL(63, 32)



#define GICR_INVLPIR_VPEID		GENMASK_ULL(47, 32)

#define GICR_INVLPIR_V			GENMASK_ULL(63, 63)



#define GICR_INVALLR_VPEID		GICR_INVLPIR_VPEID

#define GICR_INVALLR_V			GICR_INVLPIR_V



#define GIC_V3_REDIST_SIZE		0x20000



#define LPI_PROP_GROUP1			(1 << 1)

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