Commit b4931afc authored May 22, 2019 by Marc Zyngier

KVM: arm/arm64: vgic-its: Invalidate MSI-LPI translation cache on disabling LPIs



If a vcpu disables LPIs at its redistributor level, we need to make sure
we won't pend more interrupts. For this, we need to invalidate the LPI
translation cache.

Tested-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>

parent 0c144848

virt/kvm/arm/vgic/vgic-mmio-v3.c

+3 −1

Original line number	Diff line number	Diff line
		@@ -192,8 +192,10 @@ static void vgic_mmio_write_v3r_ctlr(struct kvm_vcpu *vcpu,

		vgic_cpu->lpis_enabled = val & GICR_CTLR_ENABLE_LPIS;

		if (was_enabled && !vgic_cpu->lpis_enabled)
		if (was_enabled && !vgic_cpu->lpis_enabled) {
		vgic_flush_pending_lpis(vcpu);
		vgic_its_invalidate_cache(vcpu->kvm);
		}

		if (!was_enabled && vgic_cpu->lpis_enabled)
		vgic_enable_lpis(vcpu);

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